參數(shù)資料
型號(hào)： STLC5411FN
廠商： 意法半導(dǎo)體
英文描述： 2B1Q U INTERFACE DEVICE
中文描述： 2B1Q U接口裝置
文件頁(yè)數(shù)： 5/72頁(yè)
文件大?。?/td> 739K
代理商： STLC5411FN
GENERAL DESCRIPTION
STLC5411 is a complete monolithic transceiver
for ISDN Basic access data transmission on
twisted pair subscriber loops typical of public
switched telephone networks. The device is fully
compatible with both ANSI T1.601-1988U.S. and
CSE (C32-11) French specifications. It is in-
tended also to comply with ETSI specification
bothin term of transmissionperformances and re-
quested features.
The equivalent of 160 kbit/s full-duplex transmis-
sion on a single twisted pair is provided, accord-
ing to the formats defined in the a.m. spec.
Frames include two B channels,each of 64 kbit/s,
one D channel of 16 kbit/s plus an additional 4
kbit/s M channel for loop maintenance and other
user functions. 12 kbit/s bandwidth is reserved for
framing.2B1Q Line coding is used, where pairs of
bits are coded into one of 4 quantum levels. This
technique results in a low frequency spectrum
(160 kbit/s turn into 80 kband), thereby reducing
both line attenuation and crosstalk and achieving
long range with low Bit Error Rates.
The system is designed to operate on standard
types of cable pairs including mixed gauges (26
AWG, 24 AWG and 22 AWG) including the 15
loops configuration specified by ANSI. Good
noise margins are achieved even when bridged
taps are present. On 26 AWG cable, the trans-
mission range is in excess of 5.5 km (18 kft) in
presence of crosstalk and noise as specified by
ANSI standard.STLC5411 is designed to operate
with Bit Error Rate near-end Crosstalk (NEXT) as
specifiedin europeanETSI recommendation.
To meet these very demanding specifications, the
device includes two Digital Signal Processors,
one configured as an adaptive Echo-Canceller to
cancel the near end echoes resulting from the
transmit/receive hybrid interface, the other as an
adaptive line equalizer. A Digital Phase-Locked
Loop (DPLL) timing recovery circuit is also in-
cluded that provides in NT modes a 15.36 MHz
synchronized clock to the rest of the system.
Scrambling and descrambling are performed as
specifiedin theUS and French specifications.
On the system side, STLC5411 can be linked to
twobus configurationsimply by pin MW bias.
MICROWIRE(
μ
W/DSI)
mode (MWpin = 5V): 144
kbit/s 2B+D basic access data is transferred on a
multiplex Digital System Interface with 4 different
interface formats (see fig. 2 and 3) providing
maximum flexibility with a limited pin count
(BCLK, Bx, Br, FSa, FSb). Three pre-defined
2B+D formats plus an internal time slot assigner
allows direct connection of the UID to the most
common multiplexed digital interfaces (TDM/IDL).
Bit and Frame Synchronisation signals are inputs
or outputs depending on the configuration se-
lected. Data buffers allow any phase between the
line and the digital interface. That permits building
of slave-slave configurations e.g. in NT12 trunk-
cards.
It is possible to separate the D from the B chan-
nels and to transfer it on a separate digital inter-
face (Dx, Dr) using the same bit and frame clocks
as for the B channelsor in a continuousmode us-
ing an internally generated 16 kHz bit clock output
(DCLK).
All the Control, Status and Interrupt registers are
handled via a controlchannel on a separate serial
interface MICROWIRE compatible (CI, CO, CS,
CCLK, INT) supported by a number of microcon-
troller including the MCU families from SGS-
THOMSON
GCI
mode (MWpin = 0V). Control/maintenance
channels are multiplexed with 2B+D basic access
data in a GCI compatibleinterface format (see fig.
4a) requiring only 4 pins (BCLK, Bx, Br, FSa). On
chip GCI channel assignement allows to multiplex
on thesame bus up to 8 GCI channels,each sup-
porting data and controls of one device. Bit and
Frame Synchronisation signals can be inputs or
ouputs depending on the configuration selected.
Data buffers, again, allow to have any phase be-
tween the line interfaceand the digital interface.
Through the M channel and its protocol allowing
to check both direction exchanges, internal regis-
ters can be configured, the EOC channel and the
Overhead-bits can be monitored. Associated to
the M channel, there are A and E channels for
enabling the exchanged messages and to check
the flow control. The C/I channelallows the primi-
tive exchangesfollowing the standard protocol.
In both mode (
μ
W and GCI) CRC is calculated
and checkedin both directionsinternally.
In LT mode, the transmit superframe can be syn-
chronized by an external signal (SFSx) or be self
running. In NT mode, the SFSx is always output
synchronizedby the transmit superframe.
Line side or Digital Interface side loopbacks can
be selected for each B1, B2 or D channel inde-
pendently without restriction in transparent or in
non-transparent mode. A transparent complete
analog loopback allowing the test of the transmis-
sion path is also selectable.
Activation and deactivationprocedures,which are
automatically processed by UID, require only the
exchange of simple commands as Activation Re-
quest, Deactivation Request, Activation Indica-
tion. Cold and Warm start up proceduresare op-
erated
automatically
instruction.
Four programmable I/Os are provided in GCI for
externaldevice control.
without
any
special
STLC5411
5/72
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