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參數(shù)資料
| 型號： | STLC3055QTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT |
| 中文描述： | 環(huán)路 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 153K |
| 代理商： | STLC3055QTR |
shaping by thecapacitorCS.
The waveform so generated is then filtered and
injectedon the line.
The low pass filter can be obtainedusingthe inte-
grated buffer OP1 connected between pin FTTX
(OP1 non inverting input) and RTTX (OP1 output)
(see fig.4) and implementing a ”Sallen and Key”
configuration.
Dependingon the external components count it is
possible to build an optimised
pending on the distortion level required. In par-
ticular harmonic distortion levels equal to 13%,
6% and 3% can be obtained respectively with
first,second and thirdorder filters (see fig.4).
The circuit showed in the ”Application diagram” is
relatedto the simple first orderfilter.
Once the shaped and filtered signal is obtained at
RTTX buffer output it is injected on the TIP/RING
pins with a +6dB gain.
It should be noted that this is the nominal condi-
tion obtained in presence of ideal TTX echo can-
cellation(obtained via proper settingof RTTX and
CTTX). In addition the effective level obtained on
the line will depend on the line impedance, the
protection resistor value and the series switch
(SW1 or SW2)on resistance.
In the typical application (TTX line impedance
=200
, RP = 41
, SW1,2 on resistance = 9
and ideal TTX echo cancellation) the metering
pulse level on the line will be 1.33 times the level
appliedto theRTTX pin.
application de-
As already mentioned the metering pulse echo
cancellationis obtainedby means of two external
components(RTTXand CTTX) that should match
the line impedance at the TTX frequency. This
simplenetwork has a doubleeffect:
Synthesise a low output impedance at the
TIP/RINGpins at the TTX frequency.
Cut the eventual TTX echo that will be trans-
ferredfrom the line to the TX output.
Ringing
When this mode is selected STLC3055 self gen-
erate an higher negative battery (-70V typ.) in or-
der to allow a balanced ringing signal of typically
65Vpeak.
In this condition both the DC and AC feedback
loop are disabled and the SLIC line drivers oper-
ateas voltagebuffers.
The ring waveform is obtained toggling the D2
controlbit at the desired ring frequency.This bit in
fact controls the line polarity (0=direct; 1=re-
verse). As in the ACTIVE mode the line voltage
transition is performed with a ramp transition, ob-
taining in this way a trapezoidal balanced ring
waveform(seefig.5).
The shaping is defined by the CREV external
capacitor.
Selecting the proper capacitor value it is possible
to get differentcrest factorvalues.
The following table shows the crest factor values
CTTX1
CTTX2
CS
RLV
SQTTX
RLV
BURST
SHAPING
GENERATOR
D0
CKTTX
Square wavepulse metering
Sinusoidalwave
pulsemetering
RTTX
FTTX
Low Pass Filter
-
+
OP1
CFL
R1
R2
C2
C1
Required externalcomponents vs. filter order.
Figure 4. Meteringpulse generation circuit.
Order CFL
R1
C!
R2
C2
THD
1
X
13%
2
X
X
X
X
6%
3
X
X
X
X
X
3%
STLC3055
7/22
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