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參數(shù)資料
| 型號： | STLC3055QTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT |
| 中文描述： | 環(huán)路 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大小： | 153K |
| 代理商： | STLC3055QTR |
these applications is the integrated ringing gener-
ator.
The control interface is a parallel type with open
drain output and 3.3V logiclevels.
The metering pulses are generatedon chip start-
ing from two logic signals (0, 3.3V) one define the
metering pulse frequency and the other the me-
tering pulse duration. An on chipcircuit then pro-
vides the proper shaping and filtering. Metering
pulse amplitude and shaping (rising and decay
time) can be programmed by external compo-
nents. A dedicated cancellation circuit avoid pos-
sible CODEC input saturation due to Metering
pulse echo.
Constant current feed can be set from 20mA to
40mA. Off-hook detection threshold is program-
mable from5mA to 9mA.
The device, developed in BCD100II technology
(100V process), operates in the extended tem-
perature range and integrates a thermal protec-
tion that sets the device in power down when Tj
exceeds140
°
C.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
pos
Positive Supply Voltage
-0.4 to +17
V
A/BGND
AGND to BGND
-1 to +1
V
V
dig
Pin D0, D1, D2, DET, CKTTX
-0.4 to 5.5
V
T
j
Max. junction Temperature
150
°
C
V
btot(1)
Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device
supply pins).
100
V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
1
2
3
5
6
4
7
8
9
10
17
11
18
19
20
21
22
44
43
42
41
39
40
38
37
36
35
34
28
27
26
24
23
25
33
32
31
29
30
N.C.
RES
PD
D1
D0
D2
CTTX2
CTTX1
CKTTX
N.C.
DET
R
F
R
Z
R
Z
Z
C
T
V
C
V
C
N
T
N
N
N
R
N
V
B
RLIM
AGND
CVCC
RSENSE
GATE
VPOS
CSVR
ILTF
RD
IREF
RTH
D97TL279A
12
13
14
15
16
PIN CONNECTION
DESCRIPTION
(continued)
STLC3055
2/22
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