參數(shù)資料
型號(hào)： STK6005F
廠商： Electronic Theatre Controls, Inc.
英文描述： converting PC / Mac video images for a TFT-LCD display monitor
中文描述： 轉(zhuǎn)換電腦/蘋(píng)果的視頻圖像的TFT液晶顯示屏
文件頁(yè)數(shù)： 27/36頁(yè)
文件大?。?/td> 391K
代理商： STK6005F
27
STK6005
0x1D
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
SelDE
EnYUV
SetVref
SetHref
SetCref
SetField
YUV16
SelLLC2
VSDelay
0
0
0
0
0
0
0
0
R/W 0/1 : to select register setting / ExtDE as display active
1 : to select a YUV input
0/1 : to set Vref polarity to positive / negative
0/1 : to set Href polarity to positive / negative
0/1 : to set Cref polarity to positive / negative
0/1 : to set Field (Odd) polarity to positive / negative
0/1 : video format is a 8-bit (CCIR 656) / 16-bit format.
1 : to select LLC2 as input clock
R/W Delay of internal Vsync (* 8 input clocks)
0x1E
0x04
6.2 Panel Window Control
Address
0x20
[7:0]
0x21
[3:0]
0x22
[7:0]
0x23
[3:0]
0x24
[7:0]
0x25
[3:0]
0x26
[7:0]
0x27
[3:0]
0x28
[7:0]
0x29
[3:0]
0x2A
[7:0]
0x2B
[7:0]
0x2C
[7:0]
0x2D
[2:0]
0x2E
[7:0]
0x2F
[2:0]
0x30
[7:0]
0x31
[2:0]
0x32
[7:0]
0x33
[2:0]
0x34
[7:0]
0x35
[2:0]
Bit
Name
Initial R/W
0x28
0x1
0x28
0x5
0x28
0x1
0x28
0x5
0x40
0x5
0x88
0x06
0x23
0x0
0x23
0x3
0x23
0x0
0x23
0x3
0x26
0x3
Description
PHDE1[7:0]
PHDE1[11:8]
PHDE2[7:0]
PHDE2[11:8]
PHXDE1[7:0]
PHXDE1[11:8]
PHXDE2[7:0]
PHXDE2[11:8]
PHT[7:0]
PHT[11:8]
PHSW[7:0]
PVSW[7:0]
PVDE1[7:0]
PVDE1[10:8]
PVDE2[7:0]
PVDE2[10:8]
PVXDE1[7:0]
PVXDE1[10:8]
PVXDE2[7:0]
PVXDE2[10:8]
PVT[7:0]
PVT[10:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Panel horizontal sync width (# of PCLKs)
R/W Panel vertical sync width (# of lines)
R/W Panel vertical DE start position (# of lines)
R/W
R/W Panel vertical DE end position (# of lines)
R/W
R/W Panel vertical image start position (# of lines)
R/W
R/W Panel vertical image end position (# of lines)
R/W
R/W
R/W
set PVT = 0x7FF if EnSyncH/V = 1
Panel horizontal DE start position (# of PCLKs)
Panel horizontal DE end position (# of PCLKs)
Panel horizontal image start position (# of PCLKs)
Panel horizontal image end position (# of PCLKs)
Panel horizontal total (# of PCLKs)
set PHT = 0xFFF if EnSyncH = 1
Panel vertical total (# of lines)
6.3 Scaling Control
Address
0x36
0x37
0x38
0x39
0x3A
0x3B
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Name
HSR[7:0]
HSR[15:8]
VSR[7:0]
VSR[15:8]
EmPHT[7:0]
EmPHT[15:8]
Initial R/W
0x00
0x80
0x00
0x80
0x00
0x54
Description
R/W
R/W
R/W
R/W
R/W
R/W
Horizontal expansion ratio = (INres / OUTres) *32768
Vertical expansion ratio = (INres / OUTres) * 32768
Emulate PHT by input clocks = (Panel H period / input
clock period) * 16
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