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參數(shù)資料
| 型號： | STK6005F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | converting PC / Mac video images for a TFT-LCD display monitor |
| 中文描述： | 轉(zhuǎn)換電腦/蘋果的視頻圖像的TFT液晶顯示屏 |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 391K |
| 代理商： | STK6005F |
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STK6005
Buffer Status Detection
STK6005 detects the operation of internal buffer and provides the information to correctly synchronize the input
and output image. The registers of buffer status are shown below:
1. OverRun: This flag is set to 1 when the input rate of input image is larger than the output rate. Some input
video data are overwritten before output.
2. UnderRun: This flag is set to 1 when the output rate of output image is larger than the input rate. Some
input video data are not available for output.
3. BufUsage: This 16-bit value indicates the maximum buffer usage. A bit 15 is also an indicator for underrun.
Bits 14 to 11 indicate the maximum line usage of internal buffer. Bits 10 to 0 indicate the pixel
usage of internal buffer.
4. PosVXDE: This 11-bit value indicates the vertical position (lines) of input image stored in the internal
buffer when STK6005 starts to output the first video data of a frame. This value should be
in range of 3 – 5 for a correct input-output synchronization.
5. PosHXDE: This 11-bit value indicates the horizontal position (pixels) of input image stored in internal
buffer when STK6005 starts to output the first video data of a frame.
5.15 I
2
C Interface
STK6005 supports the industrial 2-wire serial bus interface to communicate with external micro-controller.
The interface consists of an input pin SCL for serial clock and a bi-directional pin SDA for input / output
data. The slave address of this chip is 1111010x (F4H for write and F5H for read operations). The I2C
block will auto-increase the register address after each data write-in or read-out. For the operation timing
and protocol, please refer to the 2-wire serial bus specification.
5.16 Interrupt
STK6005 provides 8 interrupt flags to tell the micro-controller when the defined internal events happen.
The INTN pin will output low when any interrupt flag is being set. The interrupt flag register indicates
what events trigger the interrupt. To write data to the interrupt enable register (0x7F) will automatically
Video
P5
Level
P1 P2 P3 P4 P5
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