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參數(shù)資料
| 型號： | STK17T88-RF45 |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | PROGRAMMABLE TIMER, PDSO48 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, SSOP-48 |
| 文件頁數(shù)： | 5/29頁 |
| 文件大?。?/td> | 535K |
| 代理商： | STK17T88-RF45 |
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13
STK17T88
Jan, 2008
Document Control #ML0024 Rev 2.0
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
HARDWARE STORE (HSB) OPERATION
The STK17T88 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK17T88 will conditionally initiate a STORE opera-
tion after tDELAY. An actual STORE cycle will only
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin has a
very resistive pullup and is internally driven low to
indicate a busy condition while the STORE (initiated
by any means) is in progress. This pin should be
externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK17T88 will
continue to allow SRAM operations for tDELAY. Dur-
ing tDELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is
pulled low, it will be allowed a time, tDELAY, to com-
plete.
However,
any
SRAM
WRITE
cycles
requested after HSB goes low will be inhibited until
HSB returns high.
During any STORE operation, regardless of how it
was initiated, the STK17T88 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE opera-
tion, the STK17T88 will remain disabled until the
HSB
pin returns high.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(VCC<VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automati-
cally be initiated and will take tHRECALL to complete.
SOFTWARE STORE
Data can be transferred from the SRAM to the non-
volatile memory by a software address sequence.
The STK17T88 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations in exact order. During
the STORE cycle, previous data is erased and then
the new data is programmed into the nonvolatile ele-
ments. Once a STORE cycle is initiated, further
memory inputs and outputs are disabled until the
cycle is completed.
To initiate the software STORE cycle, the following
READ sequence must be performed:
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence. After the tSTORE cycle time has been ful-
filled, the SRAM will again be activated for READ
and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile mem-
ory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL
cycle, the following sequence of E controlled READ
operations must be performed:
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time, the SRAM will once
again be ready for READ or WRITE operations. The
RECALL
operation in no way alters the data in the
nonvolatile storage elements.
1 Read A ddress 0x0E38 V alid REA D
2 Read A ddress 0x31C7 V alid REA D
3 Read A ddress 0x03E0 V alid REA D
4 Read A ddress 0x3C1F V alid REA D
5 Read A ddress 0x303F V alid REA D
6 Read A ddress 0x0FC0 Initiate STORE Cycle
1 Read A ddress 0x0E38 V alid REA D
2 Read A ddress 0x31C7 V alid REA D
3 Read A ddress 0x03E0 V alid REA D
4 Read A ddress 0x3C1F V alid REA D
5 Read A ddress 0x303F V alid REA D
6 Read A ddress 0x0C63 Initiate RECA LL Cycle
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STK17T88-RF25ITR | PROGRAMMABLE TIMER, PDSO48 |
| STK17TA8-R25I | REAL TIME CLOCK, PDSO48 |
| STK17TA8-R35 | REAL TIME CLOCK, PDSO48 |
| STK17TA8-W25 | REAL TIME CLOCK, PDIP40 |
| STK17TA8-R45 | REAL TIME CLOCK, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STK17T88-RF45I | 功能描述:NVRAM 32Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK17T88-RF45ITR | 功能描述:NVRAM 32Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK17T88-RF45TR | 功能描述:NVRAM 32Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK17TA8-RF25 | 功能描述:NVRAM 128Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK17TA8-RF25I | 功能描述:NVRAM 128Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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