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參數(shù)資料
| 型號(hào)： | STEL-1375A+80 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP35 |
| 封裝： | 2.500 X 1.300 INCH, 0.350 INCH HEIGHT, DIP-35 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 202K |
| 代理商： | STEL-1375A+80 |
STEL-1375A+80
10
APPLICATIONS INFORMATION
Since the STEL-1375A+80 combines high-speed digital
and analog circuits, care must be taken to minimize the
effects of noise from the digital circuit on the analog
output. The following precautions will help in this
area:
1.
Use ground and power planes on the printed
circuit board. Separate analog and digital ground
planes will also help.
2.
Decouple the analog VEE line from the VEE supply
with a 1
H inductor.
The clock input can be either a sine wave or a square
wave, the input buffer will square up a sinusoidal
input. The input is capacitively coupled internally. A
sine wave signal at about 0 to +10 dBm (50
) is
recommended.
Ana.
GND
VSS
34
33
STEL-1375A+80
AVEE
32
DVEE
–5.2 V (Ana.)
–5.2 V (Dig.)
Dig.
GND
VSS
1, 4,
21, 29
VDD
5, 27,
31
+5 V
USING THE STEL-1375A+80
IN A HIGH-SPEED PHASE
MODULATOR
By routing the data and address lines
from the microcontroller via 2:1
multiplexers (e.g. 74HC157) the
MNCO can be set up from the
microcontroller and then phase
modulated at high-speed from an
external source.
The PHSEL line
should be set to a logic 0 to enable this
mode of operation. The system shown
modulates all 12 bits. In a typical PSK
system only 1 to 4 bits of modulation
will be used, simplifying the system
considerably.
FROM
PHASE
MOD.
DATA 0-7
0-3
ADDR
PHASE0-11
FREQ./PH SEL
A
B
A/B
A
B
A/B
A
B
A/B
D0
D3
D4
D7
A0
A3
.
PHLD
FROM
C
STEL-1375A
DDS
PHASE LOAD
FREQ. LOAD
WRITE
WRSTB
FRLD
4
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