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參數(shù)資料
| 型號： | STDS75M2F |
| 廠商： | 意法半導體 |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Digital temperature sensor and thermal watchdog |
| 中文描述： | 數(shù)字溫度傳感器和熱看門狗 |
| 文件頁數(shù)： | 14/37頁 |
| 文件大?。?/td> | 204K |
| 代理商： | STDS75M2F |
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Operation
STDS75
14/37
2.5
Fault tolerance
For both Comparator and Interrupt modes, the alarm “fault tolerance” setting plays a role in
determining when the OS/INT output will be activated. Fault tolerance refers to the number
of consecutive times an error condition must be detected before the user is notified. Higher
fault tolerance settings can help eliminate false alarms caused by noise in the system. The
alarm fault tolerance is controlled by the bits (Bits 4 and 3) in the Configuration Register.
These bits can be used to set the fault tolerance to 1, 2, 4, or 6 as shown in
Table 2
. At
power-up, these bits both default to logic '0.'
Table 2.
2.6
Shutdown mode
For power-sensitive applications, the STDS75 offers a low-power shutdown mode. The SD
Bit in the Configuration register controls shutdown mode. When SD is changed to login '1,'
the conversion in progress will be completed and the result stored in the temperature
register, after which the STDS75 will go into a low-power standby state. The OS/INT output
will be cleared if the thermostat is operating in Interrupt mode and the OS/INT will remain
unchanged in Comparator mode. The 2-wire interface remains operational in shutdown
mode, and writing a '0' to the SD Bit returns the STDS75 to normal operation.
Fault tolerance setting
FT1
FT0
STDS75 (Consecutive Faults)
Comments
0
0
1
Power-up default
0
1
2
1
0
4
1
1
6
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