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| 型號(hào)： | STDH90 |
| 英文描述： | Leaded Cartridge Fuse; Current Rating:62.5mA; Voltage Rating:250V; Fuse Terminals:Axial Lead; Fuse Type:Time Delay; Voltage Rating:250V; Body Material:Ceramic; Diameter:6.985mm; Fuse Size/Group:1/4 x 1-1/4 " RoHS Compliant: Yes |
| 中文描述： | STDH90 0.35微米STDH90圖書館|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 23/122頁 |
| 文件大?。?/td> | 277K |
| 代理商： | STDH90 |
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1.13 VDD/VSS Rules and Guidelines
Introduction
STDH90/MDL90
1-17
SEC ASIC
V
DD
/V
SS
buses and pads should be distributed evenly in the core and on
all sides of the chip.
pads
The total number of core logic V
DD
I pads required is equal to that of VSSI
The number of VSSI/VDDI pad pairs required for a design can be calculated
from the following expression:
The number of VDDI/VSSI pad pairs =
|| (G x S x F x GC
eq_current
) + {
∑
(P_i x F_i)} / I
em
|| round-up
In the above formula,
G = The core ( excluding hard macro blocks) size in gate counts
S = % of simultaneous switching gates (default = 0.2)
F = Switching frequency (MHz)
GC
eq_current
= Equivalent power(current) per gate(0.101uW/MHz/V)
P_i = Characterized power (current) for the i-th hard macro block(mA/MHz)
F_i = Switching frequency for the i-th hard macro block(MHz)
l
em
= Current limit per Vdd/Vss pad pairs based on electromigration rule.
(100mA)
For reliable device operation and minimum IR voltage drop, minimum number
of VSSI/VDDI pad pairs is 4.
Extra power may be needed for the demanding high power macro blocks
(SRAM,analog block,and so on)
1.13.3 Input Buffer V
DD
/V
SS
Pad VDDP/VSSP Allocation
Guidelines
These guidelines ensure that an adequate input threshold voltage margin is
maintained during a switching.
The number of VSSP/VDDP pad pairs required for a design can be
calculated from the following expression:
The number of VDDP/VSSP pad pairs =
|| Ieq_p / I
em
||round-up
in the above formula,
Ieq_p =
∑
(Average current of input buffers and output pre-drivers
at maximum operating frequency)
l
em
= Current limit per Vdd/Vss pad pairs based on electro-migration rule.
(100 mA)
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