
SEC ASIC
3-378
MDL110
FDS3/FDS3D2
D Flip-Flop with Synchronous Set, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements
(Typical process, 25
°
C, 2.5V, Unit = ns)
Value (ns)
FDS3
0.484
0.096
0.363
0.132
0.378
0.319
Input Load (SL)
Gate Count
FDS3
FDS3
CSN
0.5
FDS3D2
CSN
0.5
FDS3D2
D
0.6
CK
0.6
D
0.6
CK
0.6
6.00
6.67
Parameter
Symbol
FDS3D2
0.484
0.095
0.364
0.131
0.380
0.338
Input Setup Time (D to CK)
Input Hold Time (D to CK)
Input Setup Time (CSN to CK)
Input Hold Time (CSN to CK)
Pulse Width Low (CK)
Pulse Width High (CK)
t
SU
t
HD
t
SU
t
HD
t
PWL
t
PWH
D
CSN
CK
Q
QN
CL
CLB
Q
CLB
CL
CLB
CL
QN
D
CK
CL
CLB
CSN
CL
CLB
Truth Table
D
0
1
x
x
CSN
1
1
0
x
CK
Q (n+1) QN (n+1)
0
1
1
Q (n)
1
0
0
QN (n)