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STD110
4-110
SEC ASIC
POT1/2/4/8_ABB
Analog Tri-state Output Buffers with Enable Port and Separate Bulk-Bias
Switching Characteristics
(Typical process, 25
°
C, 2.5V, t
R
/t
F
= 0.17ns, CL: Capacitive Load)
POT2_ABB
Switching Characteristics
(Typical process, 25
°
C, 2.5V, t
R
/t
F
= 0.17ns, CL: Capacitive Load)
POT4_ABB
Path
Parameter
Delay [ns]
CL = 50.0pF
16.047
18.535
8.431
10.353
16.047
18.535
8.479
10.477
0.808
0.768
16.047
18.535
8.581
10.580
0.851
0.810
<
Delay Equations [ns]
Group1*
0.897 + 0.303*CL
1.010 + 0.350*CL
1.177 + 0.145*CL
1.235 + 0.182*CL
0.897 + 0.303*CL
1.010 + 0.350*CL
1.224 + 0.145*CL
1.357 + 0.182*CL
0.808 + 0.000*CL
0.768 + 0.000*CL
0.897 + 0.303*CL
1.010 + 0.350*CL
1.327 + 0.145*CL
1.460 + 0.182*CL
0.851 + 0.000*CL
0.810 + 0.000*CL
Group2*
0.899 + 0.303*CL
1.011 + 0.350*CL
1.177 + 0.145*CL
1.233 + 0.182*CL
0.899 + 0.303*CL
1.011 + 0.350*CL
1.224 + 0.145*CL
1.357 + 0.182*CL
0.808 + 0.000*CL
0.768 + 0.000*CL
0.899 + 0.303*CL
1.011 + 0.350*CL
1.327 + 0.145*CL
1.462 + 0.182*CL
0.851 + 0.000*CL
0.810 + 0.000*CL
Group3*
0.899 + 0.303*CL
1.011 + 0.350*CL
1.177 + 0.145*CL
1.236 + 0.182*CL
0.899 + 0.303*CL
1.011 + 0.350*CL
1.228 + 0.145*CL
1.360 + 0.182*CL
0.808 + 0.000*CL
0.768 + 0.000*CL
0.899 + 0.303*CL
1.011 + 0.350*CL
1.327 + 0.145*CL
1.462 + 0.182*CL
0.851 + 0.000*CL
0.810 + 0.000*CL
A to PAD
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tPLZ
tPHZ
tR
tF
tPLH
tPHL
tPLZ
tPHZ
TN to PAD
EN to PAD
*Group1 : CL < 50, *Group2 : 50 =
Path
Parameter
Delay [ns]
CL = 50.0pF
8.054
9.284
4.795
5.607
8.054
9.284
4.842
5.729
0.940
0.978
8.054
9.284
4.945
5.832
0.982
1.020
<
Delay Equations [ns]
Group1*
0.484 + 0.151*CL
0.522 + 0.175*CL
1.167 + 0.073*CL
1.048 + 0.091*CL
0.484 + 0.151*CL
0.522 + 0.175*CL
1.214 + 0.073*CL
1.168 + 0.091*CL
0.940 + 0.000*CL
0.978 + 0.000*CL
0.484 + 0.151*CL
0.522 + 0.175*CL
1.318 + 0.073*CL
1.271 + 0.091*CL
0.982 + 0.000*CL
1.020 + 0.000*CL
Group2*
0.480 + 0.151*CL
0.521 + 0.175*CL
1.168 + 0.073*CL
1.048 + 0.091*CL
0.480 + 0.151*CL
0.521 + 0.175*CL
1.215 + 0.073*CL
1.169 + 0.091*CL
0.940 + 0.000*CL
0.978 + 0.000*CL
0.480 + 0.151*CL
0.521 + 0.175*CL
1.318 + 0.073*CL
1.272 + 0.091*CL
0.982 + 0.000*CL
1.020 + 0.000*CL
Group3*
0.480 + 0.151*CL
0.522 + 0.175*CL
1.168 + 0.073*CL
1.048 + 0.091*CL
0.480 + 0.151*CL
0.522 + 0.175*CL
1.216 + 0.073*CL
1.170 + 0.091*CL
0.940 + 0.000*CL
0.978 + 0.000*CL
0.480 + 0.151*CL
0.522 + 0.175*CL
1.318 + 0.073*CL
1.274 + 0.091*CL
0.982 + 0.000*CL
1.020 + 0.000*CL
A to PAD
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tPLZ
tPHZ
tR
tF
tPLH
tPHL
tPLZ
tPHZ
TN to PAD
EN to PAD
*Group1 : CL < 50, *Group2 : 50 =