參數(shù)資料
型號(hào): STCN75DS2E
廠商: 意法半導(dǎo)體
元件分類: 溫度/濕度傳感器
英文描述: Digital temperature sensor and thermal watchdog
中文描述: 數(shù)字溫度傳感器和熱看門狗
文件頁數(shù): 20/35頁
文件大?。?/td> 194K
代理商: STCN75DS2E
Functional description
STCN75
20/35
3.4.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
Figure 5.
Serial bus data transfer sequence
3.4.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse (see
Figure 6 on page 21
). A slave receiver which is addressed is
obliged to generate an acknowledge after the reception of each byte that has been clocked
out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line High to enable the master to generate the
STOP condition.
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
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