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參數(shù)資料
| 型號： | STA003 |
| 英文描述： | MPEG 2.5 LAYER III AUDIO DECODER |
| 中文描述： | 2.5第三層的MPEG音頻解碼器 |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 299K |
| 代理商： | STA003 |
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3.4 - READ OPERATION
(see Fig. 10)
3.4.1 - Current byte address read
The STA003T has an internal byte address
counter. Each time a byte is written or read, this
counter is incremented.
For the current byte address read mode, follow-
ing a START condition the master sends the de-
vice address with the RW bit set to 1.
The STA003T acknowledges this and outputs the
byte addressed by the internal byte address
counter. The master does not acknowledge the
received byte, but terminates the transfer with a
STOP condition.
3.4.2 - Sequential address read
This mode can be initiated with either a current
address read or a random address read. How-
ever in this case the master does acknowledge
the data byte output and the STA003T continues
to output the next byte in sequence.
To terminate the streams of bytes the master
does not acknowledge the last received byte, but
terminates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after one byte output.
4 - I
2
C REGISTERS
The following table gives a description of the
MPEG Source Decoder (STA003T) register list.
The first column (HEX_COD) is the hexadecimal
code for the sub-address.
The second column (DEC_COD) is the decimal
code.
The third column (DESCRIPTION) is the descrip-
tion of the information contained in the register.
The fourth column (RESET) inidicate the reset
value if any. When no reset value is specifyed,
the default is "undefined".
The fifth column (R/W) is the flag to distinguish
register "read only" and "read and write", and the
useful size of the register itself.
Each register is 8 bit wide. The master shall oper-
ate reading or writing on 8 bits only.
I
2
C REGISTERS
HEX_COD
0x00
0x01
0x05
0x06
0x07
0x0B
0x0C
0x0D
0x0F
DEC_COD
0
1
5
6
7
11
12
13
15
DESCRIPTION
RESET
R/W
R (8)
R (8)
R/W (8)
R/W (8)
R/W (8)
VERSION
IDENT
PLLCTL [7:0]
PLLCTL_M
PLLCTL_N
reserved
reserved
SCLK_POL
ERROR_CODE
0xAC
0x21
0x0C
0x00
0x04
0x00
R/W (8)
R (8)
DEV-ADDR
ACK
START
D98AU826A
RW
DATA
NO ACK
STOP
CURRENT
ADDRESS
READ
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
STOP
RANDOM
ADDRESS
READ
DATA
NO ACK
START
RW
DEV-ADDR
ACK
START
DATA
ACK
DATA
ACK
STOP
SEQUENTIAL
CURRENT
READ
DATA
NO ACK
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
SEQUENTIAL
RANDOM
READ
DATA
ACK
START
RW
DATA
ACK
NO ACK
STOP
DATA
RW=
HIGH
Figure 10.
Read Mode Sequence
STA003T
10/32
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STA10 | ASIC |
| STA351A | General Purpose Sink Driver Array |
| STA352A | General Purpose Source Driver Array |
| STA474A | H-bridge Motor Driver Array |
| STB100NF03L-03T4 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 100A I(D) | TO-263AB |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STA003T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MPEG 2.5 LAYER III AUDIO DECODER |
| STA011 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:L-band RF front-end for digital radio |
| STA011E | 制造商:ST 功能描述:DAB |
| STA013 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MPEG 2.5 LAYER III AUDIO DECODER |
| STA013 | 功能描述:音頻 DSP MPEG Audio Decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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