參數(shù)資料
型號(hào)： ST95P02M1
廠商： 意法半導(dǎo)體
英文描述： SPI Serial EEPROM
中文描述： SPI串行EEPROM
文件頁(yè)數(shù)： 8/16頁(yè)
文件大?。?/td> 151K
代理商： ST95P02M1
Read Status Register (RDSR)
The RDSR instruction provides access to the status
register. The status register may be read at any
time, even during a non-volatile write. As soon as
the 8th bit of the status register is read out, the
ST95P02 enters a wait mode (data on D are not
decoded, Q is in Hi-Z) until it is deselected.
The status register format is as follows:
b7
b0
1
1
1
1
BP1
BP0
WEL
WIP
BP1, BP0: Read and Write bits
WEL, WIP: Read only bits.
During a non-volatile write to the memory array, all
bits BP1, BP0, WEL, WIP are valid and can be read.
During a non volatile write to the status register, the
only bits WEL and WIP are valid and can be read.
The values of BP1 and BP0 read at that time
correspond to the previous contents of the status
register.
The Write-In-Process (WIP) read only bit indicates
whether the ST95P02 is busy with a write opera-
tion. When set to a ’1’ a write is in progress, when
set to a ’0’ no write is in progress.
The Write Enable Latch (WEL) read only bit indi-
cates the status of the write enable latch. When set
to a ’1’ the latch is set, when set to a ’0’ the latch is
reset.
The Block Protect (BP0 and BP1) bits indicate the
extent of the protection employed. These bits are
set by the user issuing the WRSR instruction.
These bits are non-volatile.
Write Status Register (WRSR)
The WRSR instruction allows the user to select the
size of protected memory. The ST95P02 is divided
into four 512 bit blocks. The user may read the
blocks but will be unable to write within the selected
blocks.
The blocks and respective WRSR control bits are
shown in Table 6.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S. This
rising edge of S must appear after the 8th bit of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Read Operation
The chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Then, the data
stored in the memory at the selected address is
shifted out on the Q output pin; each bit being
shifted out during the falling edge of the clock (C).
The data stored in the memory at the next address
can be read in sequence by continuing to provide
clock pulses. The byte address is automatically
incremented to the next higher address after each
byte of data is shifted out.
Status Register Bits
Array Addresses
Protected
BP1
BP0
0
0
none
0
1
C0h - FFh
1
0
80h - FFh
1
1
00h - FFh
Table 6. Array Addresses Protect
Instruction
Description
Instruction Format
WREN
Set Write Enable Latch
0000 0110
WRDI
Reset Write Enable Latch
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read Data from Memory Array
0000 0011
WRITE
Write Data to Memory Array
0000 0010
Table 7. Instruction Set
8/16
ST95P02
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST95P02M1TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM
ST95P02M3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM
ST95P02M3TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM
ST95P02M6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM
ST95P02M6TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPI Serial EEPROM
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