
EraseAll
The Erase All instruction (ERAL) erases the whole
memory (all memory bits are set to ’1’). A dummy
addressis input duringthe instructiontransfer and
the erase is made in the sameway as the ERASE
instruction. If the ST93C66 is still performing the
erasecycle,theBusysignal(Q=0) willbereturned
if S isdriven high,andthe ST93C66will ignoreany
data on the bus. When the erase cycle is com-
pleted, the Ready signal (Q = 1) will indicate (if S
is driven high)that theST93C66is readyto receive
a newinstruction.
Write All
For correct operation, an ERAL instruction should
be executed before the WRAL instruction: the
WRAL instructionDOESNOTperformanautomat-
ic erase before writing. The Write All instruction
(WRAL)writes theDataInputbyteorwordtoallthe
addresses of the memory. If the ST93C66 is still
performingthe write cycle, the Busy signal (Q = 0)
will bereturnedifSisdrivenhigh,andtheST93C66
will ignore any data on the bus. When the write
cycle is completed, the Ready signal (Q = 1) will
indicate (if S is driven high) that the ST93C66 is
ready to receive a new instruction.
READY/BUSY Status
During every programming cycle (after a WRITE,
ERASE, WRALor ERALinstruction) the Data Out-
put (Q) indicates the Ready/Busy status of the
memory when the Chip Select (S) is driven High.
Once the ST93C66 is Ready, the Ready/Busy
status is available on the Data Output (Q) until a
new start bit is decoded or the Chip Select (S) is
broughtLow.
COMMON I/O OPERATION
TheDataOutput(Q)andDataInput(D)signalscan
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memorywith this connection,mostly to prevent
a shortcircuit betweenthe last enteredaddressbit
(A0) and the first data bit output by Q. The reader
may also refer to the SGS-THOMSONapplication
note”MICROWIREEEPROMCommonI/OOpera-
tion”.
CLOCKPULSE COUNTER
The ST93C66 offers a functional security filtering
glitches on the clock input (C), the Clock pulse
counter.
In a normal environment, the ST93C66expects to
receive the exact amount of data on the D input,
that is, the exact amount of clock pulses on the C
input.
In a noisy environment, the number of pulses re-
ceived (on the clock input C) may be greater than
the clockpulsesdeliveredbytheMaster(Microcon-
troller)driving the ST93C66.In such a case, a part
of the instruction is delayedby one bit (see Figure
9), andit mayinduce an erroneouswrite of dataat
a wrong address.
The ST93C66hasanon-chipcounterwhichcounts
the clock pulses from the Start bit until the falling
edge of the Chip Select signal. For the WRITE
instructions, the number of clock pulses incoming
to the countermust be exactly20 (with the Organ-
isation by 8) from the Start bitto thefalling edge of
Chip Select signal (1 Start bit + 2 bits of Op-code
+ 9 bits of Address + 8 bits of Data = 20): if so,the
ST93C66 executes the WRITE instruction; if the
number of clock pulses is not equal to 20, the
instruction will not be executed (and data will not
be corrupted).
In the same way, when the Organisationby 16 is
selected, the number of clock pulses incoming to
the countermust be exactly 27 (1 Startbit + 2 bits
of Op-code+ 8 bits of Address + 16 bits of Data =
27) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C66 executes the
WRITE instruction;if thenumber of clockpulses is
not equalto 27, theinstruction will not be executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in-
structions(WRITE, ERASE, ERAL, WRALL).
9/13
ST93C66, ST93C67