
Instruc-
tion
Description
Op-Code
x8 Org
Address
(ORG = 0)
(1)
Data
x16 Org
Address
(ORG = 1)
(1)
Data
READ
Read Data from Memory
10
A8-A0
Q7-Q0
A7-A0
Q15-Q0
WRITE
Write Data to Memory
01
A8-A0
D7-D0
A7-A0
D15-D0
EWEN
Erase/Write Enable
00
11XXX XXXX
11XX XXXX
EWDS
Erase/Write Disable
00
00XXX XXXX
00XX XXXX
ERASE
Erase Byteor Word
11
A8-A0
A7-A0
ERAL
Erase AllMemory
00
10XXX XXXX
10XX XXXX
WRAL
Write All Memory
with same Data
00
01XXX XXXX
D7-D0
01XX XXXX
D15-D0
Note:
1. X =don’t care bit.
Table 6. InstructionSet
INSTRUCTIONS
The ST93C66 has seven instructions, asshownin
Table 6.The op-codesofthe instructionsaremade
up of2 bits.The op-code isfollowed byan address
for thebyte/wordwhich is eightbitslongforthe x16
organization or nine bits long for the x8 organiza-
tion.Eachinstructionisprecededbythe rising edge
of the signal applied on the Chip Select (S) input
(assuming that tha Clock C is low). The datainput
D is thensampled upon the followingrising edges
of the clock C untill a ’1’ is sampled and decoded
by the ST93C66as a Start bit.
The ST93C66 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
inputsignals)upto themaximumratings(specified
in Table5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
codedandthe datafrom thememory istransferred
intoanoutputshiftregister.Adummy’0’bitisoutput
first, followed by the 8 bit byte or the 16 bit word
with the MSB first. Output data changes are trig-
geredby theLowtoHightransitionoftheClock(C).
The ST93C66will automaticallyincrement the ad-
dressand will clock out the next byte/wordas long
as the Chip Select input (S) is held High. In this
case the dummy ’0’ bit is NOT output between
bytes/words and a continuousstream of data can
be read.
Erase/WriteEnable and Disable
The Erase/Write Enable instruction (EWEN)
authorizesthe followingErase/Writeinstructionsto
be executed, the Erase/Write Disable instruction
(EWDS) disables the execution of the following
Erase/Write instructions. When power is first ap-
plied, the ST93C66 enters the Disable mode.
When the EWEN instruction is executed, Write
instructions remain enabled until an Erase/Write
Disableinstruction (EWDS)is executedorV
CC
falls
below the power-on reset threshold.To protect the
memory contents from accidental corruption, it is
advisabletoissuethe EWDSinstructionafterevery
write cycle.
The READ instruction is not affectedbythe EWEN
or EWDS instructions.
Erase
The Erase instruction (ERASE) programs the ad-
dressed memory byte or word bits to ’1’. Once the
addressiscorrectlydecoded,thefallingedgeofthe
Chip Select input (S) triggers a self-timed erase
cycle.
If the ST93C66 is still performingthe erase cycle,
theBusysignal(Q= 0)willbe returnedifS isdriven
high, and the ST93C66will ignoreany dataon the
bus.Whentheerase cycleiscompleted,theReady
signal (Q = 1) will indicate (if S is driven high) that
the ST93C66is ready to receive anew instruction.
Write
The Write instruction (WRITE) is followed by the
addressandthe8or16 databits tobewritten. Data
input is sampled on the Low to High transition of
the clock. Afterthe lastdata bithas been sampled,
Chip Select (S) must be brought Low before the
next rising edge of the clock (C) in order to start
the self-timed programmingcycle. If the ST93C66
is still performing the write cycle, the Busy signal
(Q = 0) will be returnedif S is driven high, and the
ST93C66will ignore any data on the bus.
6/13
ST93C66, ST93C67