參數(shù)資料
型號: ST93C06
廠商: 意法半導體
英文描述: 256 bit (16 x 16 or 32 x 8) Serial Microwire EEPROM(256位串行EEPROM)
中文描述: 256位(16 × 16或32 × 8)串行EEPROM的微型導線(256位串行EEPROM的)
文件頁數(shù): 6/15頁
文件大?。?/td> 117K
代理商: ST93C06
POWER-ON DATA PROTECTION
In orderto prevent datacorruption and inadvertent
write operations during power up, a Power On
Reset(POR)circuit resetsallinternalprogramming
circuitry and sets the device in the Write Disable
mode. When V
CC
reaches its functionalvalue, the
deviceisproperlyreset (in the Write Disablemode)
and is ready to decode and execute an incoming
instruction. A stable V
CC
must be applied before
any logic signal.
INSTRUCTIONS
The ST93C06 has seven instructions, asshownin
Table 6.The op-codesofthe instructionsaremade
up of4 bits: some instructionsuseonlythefirst two
bits, others use all four bits to define the op-code.
The op-code is followed by an address for the
byte/wordwhichis fourbits longfor thex16 organi-
zationor fivebits long forthe x8 organization.
Each instruction is precededby the rising edge of
the signal applied on the S input (assuming that
clock C and data input D are low), followed by a
first clock pulse which is ignored by the ST93C06
(optionalclock pulse for theST93C06C). The data
input D is then sampled upon the following rising
edges of the clock C untill a ’1’ is sampled and
decoded by the ST93C06 as a Start bit. Even
though the first clock pulse is ignored, it recom-
mendedto pulllow the data inputD during thisfirst
clock pulse in order to keep the timing upwardly
compatiblewith other ST93Cxx devices.
The ST93C06 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
inputsignals)upto themaximumratings(specified
in Table5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). Whena READinstruction
is received, the instruction and address are de-
codedand thedata from thememory is transferred
intoanoutputshiftregister.Adummy’0’bitisoutput
firstfollowedby the 8bitbyte orthe 16bitwordwith
the MSB first. Output data changes are triggered
by the Low to High transitionof theClock (C). The
ST93C06will automaticallyincrement the address
and will clock outthe next byte/word aslong as the
Chip Select input (S) is held High. In this case the
dummy ’0’ bit is NOT output between bytes/words
and a continuousstream of data can be read.
Erase/WriteEnable and Disable
The Erase/Write Enable instruction (EWEN)
authorizesthefollowingErase/Writeinstructionsto
be executed, the Erase/Write Disable instruction
(EWDS) disables the execution of the following
Erase/Write instructions. When power is first ap-
plied, the ST93C06 enters the Disable mode.
When the Erase/Write Enable instruction (EWEN)
isexecuted,Writeinstructionsremainenableduntil
an Erase/WriteDisable instruction(EWDS) is exe-
cuted or if the Power-on reset circuit becomes
activeduetoareducedV
CC
. Toprotectthe memory
contentsfrom accidental corruption, it is advisable
to issue the EWDS instruction after every write
cycle. The READinstruction is not affected by the
EWEN or EWDSinstructions.
Erase
The Erase instruction (ERASE) programs the ad-
dressed memory byte or word bits to ’1’. Once the
addressiscorrectlydecoded,thefallingedgeofthe
Chip Select input (S) triggers a self-timed erase
cycle.
Instruction
Description
Op-Code
x8 Org
Address
(ORG = 0)
Data
x16 Org
Address
(ORG = 1)
Data
READ
Read Data from Memory
10XX
A4-A0
Q7-Q0
A3-A0
Q15-Q0
WRITE
Write Data to Memory
01XX
A4-A0
D7-D0
A3-A0
D15-D0
EWEN
Erase/Write Enable
0011
XXXXX
XXXX
EWDS
Erase/Write Disable
0000
XXXXX
XXXX
ERASE
Erase Byte or Word
11XX
A4-A0
A3-A0
ERAL
Erase All Memory
0010
XXXXX
XXXX
WRAL
Write All Memory
with same Data
0001
XXXXX
D7-D0
XXXX
D15-D0
Note:
X = don’t care bit.
Table 6. InstructionSet
6/15
ST93C06, ST93C06C
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