
ST72321J
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1 INTRODUCTION
The ST72321J devices are members of the ST7
microcontroller family. They are based on a com-
mon industry-standard 8-bit core, featuring an en-
hanced instruction set and are available with
FLASH or ROM program memory.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
Figure 1. Device Block Diagram
8-BIT CORE
ALU
ADDRESS
AND
DATA
BUS
OSC1
VPP
CONTROL
PROGRAM
(48K / 60K Bytes)
VDD
RESE T
PORT F
PF7:6,4,2:0
TIMER A
BEEP
PORT A
RAM
(1.5 / 2K Bytes)
PORT C
10-BIT ADC
VAREF
VSSA
PORT B
PB4:0
PORT E
PE1:0
(2 bits)
SCI
TIMER B
PA7:3
(5 bits)
PORT D
PD5:0
SPI
PC7:0
(8 bits)
VSS
WATCHDOG
OSC
LVD
OSC2
MEMORY
MCC/RTC/BE EP
(5 bits)
(6 bits)
I2C
PWM ART
3