參數(shù)資料
型號: ST72F321J9T7
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, PLASTIC, TQFP-44
文件頁數(shù): 108/176頁
文件大?。?/td> 1112K
代理商: ST72F321J9T7
ST72321J
37/176
8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 21): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(fOSC2).
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 21. Power Saving Mode Transitions
8.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (fCPU)to
the available supply voltage.
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (fCPU).
In this mode, the master clock frequency (fOSC2)
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
(fCPU).
Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.
Figure 22. SLOW Mode Clock Transitions
POWER CONSUMPTION
WAIT
SLOW
RUN
ACTIVE HALT
High
Low
SLOW WAIT
HALT
00
01
SMS
CP1:0
fCPU
NEW SLOW
NORMAL RUN MODE
MCCSR
FREQU ENCY
REQUEST
fOSC2
fOSC2/2
fOSC2/4
fOSC2
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