參數(shù)資料
型號： ST72652AR4T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 93/161頁
文件大?。?/td> 2656K
代理商： ST72652AR4T1/XXX
ST72651AR6
37/161
Doc ID 7215 Rev 4
7 INTERRUPTS
7.1 INTRODUCTION
The CPU enhanced interrupt management pro-
vides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with
flexible
interrupt
priority
and
level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: RESET, TRAP, TLI
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) CPU interrupt controller.
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 8). The process-
ing flow is shown in Figure 25.
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 8. Interrupt Software Priority Levels
Figure 25. Interrupt Processing Flowchart
Interrupt software priority
Level
I1
I0
Level 0 (main)
Low
High
10
Level 1
0
1
Level 2
0
Level 3 (= interrupt disable)
1
“IRET”
RESTORE PC, X, A, CC
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
FETCH NEXT
RESET
TLI
PENDING
INSTRUCTION
I1:0
FROM STACK
LOAD PC FROM INTERRUPT VECTOR
Y
N
Y
N
Y
N
Interrupt has the same or a
lower software priority
THE INTERRUPT
STAYS PENDING
than current one
In
te
rr
up
t
h
as
a
h
ig
h
e
r
so
ftwa
re
p
ri
o
rit
y
th
an
cu
rr
en
t
o
ne
EXECUTE
INSTRUCTION
INTERRUPT
1
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