參數(shù)資料
型號: ST72652AR4T1/XXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件頁數(shù): 84/161頁
文件大?。?/td> 2656K
代理商: ST72652AR4T1/XXX
ST72651AR6
29/161
Doc ID 7215 Rev 4
RESET SEQUENCE MANAGER (Cont’d)
In stand-alone mode, the 512 CPU clock cycle de-
lay allows the oscillator to stabilize and ensures
that recovery has taken place from the Reset
state.
In USB mode the delay is 256 clock cycles count-
ed from when the PLL LOCK signal goes high.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 19. Reset Delay in Stand-alone Mode
Figure 20. Reset Delay in USB Mode
Note: For a description of Stand-alone mode and USB mode refer to Section 6.4.
512 x tCPU(STAND-ALONE)
RESET
FETCH VECTOR
DELAY
FETCH VECTOR
256 x tCPU(STAND-ALONE)
256 x tCPU(USB)
PLL Startup
RESET
time (undefined)
DELAY
400 s typ.
1
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