參數(shù)資料
型號： ST7263BK1B/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, LEAD FREE, SHRINK, PLASTIC, DIP-32
文件頁數(shù)： 25/140頁
文件大?。?/td> 1423K
代理商： ST7263BK1B/XXX
ST7263B
120/140
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.10.2 SCI - Serial Communications Interface
Subject to general operating condition for VDD, fCPU, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI
and TDO).
13.10.3 I2C - Inter IC Control Interface
Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(SDAI and SCLI).
The ST7 I2C interface meets the requirements of the Standard I2C communication protocol described in
the following table.
(Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified)
Notes:
1. Data based on standard I2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. At 4MHz fCPU, max.I
2C speed (400kHz) is not achievable. In this case, max. I2C speed will be approximately 260KHz.
Symbol
Parameter
Conditions
Standard
Baud
Rate
Unit
fCPU
Accuracy
vs. Standard
Prescaler
fTx
fRx
Communication frequency
8MHz
~0.16%
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
300
1200
2400
4800
9600
10400
19200
38400
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
~38461.54
Hz
Symbol
Parameter
Standard mode I2C
Fast mode I2C 4)
Unit
Min 1)
Max 1)
Min 1)
Max 1)
tw(SCLL)
SCL clock low time
4.7
1.3
s
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0 3)
0 2)
900 3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
20+0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
20+0.1Cb
300
th(STA)
START condition hold time
4.0
0.6
s
tsu(STA)
Repeated START condition setup time
4.7
0.6
tsu(STO)
STOP condition setup time
4.0
0.6
s
tw(STO:STA) STOP to START condition time (bus free)
4.7
1.3
s
Cb
Capacitive load for each bus line
400
pF
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