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| 型號(hào)： | ST7260E2M1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, LEAD FREE, PLASTIC, SOP-24 |
| 文件頁(yè)數(shù)： | 47/118頁(yè) |
| 文件大?。?/td> | 2304K |
| 代理商： | ST7260E2M1/XXX |
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ST7260
34/117
I/O PORTS (Cont’d)
9.2.4 Register Description
DATA REGISTERS (PxDR)
Port A Data Register (PADR): 0000h
Port B Data Register (PBDR): 0002h
Port C Data Register (PCDR): 0004h
Read/Write
Reset Value Port A: 0000 0000 (00h)
Reset Value Port B: 0000 0000 (00h)
Reset Value Port C: 1111 x000 (FXh)
Note: For Port C, unused bits (7-3) are not acces-
sible.
Bit 7:0 = D[7:0] Data Register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
Note: When using open-drain I/Os in output con-
figuration, the value read in DR is the digital value
applied to the I/Opin.
DATA DIRECTION REGISTER (PxDDR)
Port A Data Direction Register (PADDR): 0001h
Port B Data Direction Register (PBDDR): 0003h
Port C Data Direction Register (PCDDR): 0005h
Read/Write
Reset Value Port A: 0000 0000 (00h)
Reset Value Port B: 0000 0000 (00h)
Reset Value Port C: 1111 x000 (FXh)
Note: For Port C, unused bits (7-3) are not acces-
sible
Bit 7:0 = DD[7:0] Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
Table 14. I/O Ports Register Map
Related Documentation
AN 970: SPI Communication between ST7 and EEPROM
AN1048: Software LCD driver
70
D7
D6
D5
D4
D3
D2
D1
D0
70
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Address
(Hex.)
Register
Label
7
6
543
2
1
0
00
PADR
MSB
LSB
01
PADDR
MSB
LSB
02
PBDR
MSB
LSB
03
PBDDR
MSB
LSB
04
PCDR
MSB
LSB
05
PCDDR
MSB
LSB
06
Reserved
07
Reserved
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