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參數(shù)資料
| 型號： | ST72345C4T6TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, TQFP-32 |
| 文件頁數(shù)： | 82/246頁 |
| 文件大?。?/td> | 2016K |
| 代理商： | ST72345C4T6TR |
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On-chip peripherals
ST72344xx, ST72345xx
172/246
Address matched: the interface generates in sequence the following:
●
An Acknowledge pulse
●
Depending on the LSB of the slave address sent by the master, slaves enter transmitter
or receiver mode.
●
Send an interrupt to the CPU after completion of the read/write operation after
detecting the Stop/ Restart condition on the SDA line.
Note:
The Status Register has to be read to clear the event flag associated with the interrupt
An interrupt will be generated only if the interrupt enable bit is set in the Control Register
Slaves 1 and 2 have a common interrupt and the Slave 3 has a separate interrupt.
At the end of write operation, I2C3S is temporarily disabled by hardware by setting BusyW
bit in CR2. The byte count register, status register and current address register should be
saved before resetting BusyW bit.
Slave reception (write operations)
Byte Write: The Slave address is followed by an 8-bit byte address. Upon receipt of this
address an acknowledge is generated, address is moved into the current address register
and the 8 bit data is clocked in. Once the data is shifted in, a DMA request is generated and
the data is written in the RAM. The addressing device will terminate the write sequence with
a stop condition. Refer to Figure 76
Page Write: A page write is initiated in similar way to a byte write, but the addressing device
does not send a stop condition after the first data byte. The page length is programmed
using bits 7:6 (PL[1:0]) in the Control Register1.
The current address register value is incremented by one every time a byte is written. When
this address reaches the page boundary, the next byte will be written at the beginning of the
same page. Refer to Figure 77.
Slave transmission (Read operations)
Current address read: The current address register maintains the last address accessed
during the last read or write operation incremented by one.
During this operation the I2C slave reads the data pointed by the current address register.
Refer to Figure 78.
Random read: Random read requires a dummy byte write sequence to load in the byte
address. The addressing device then generates restart condition and resends the device
address similar to current address read with the read/write bit high. Refer to Figure 79.
Some types of I2C masters perform a dummy write with a stop condition and then a current
address read.
In either case, the slave generates a DMA request, sends an acknowledge and serially
clocks out the data.
When the memory address limit is reached the current address will roll over and the random
read will continue till the addressing master sends a stop condition.
Sequential read: Sequential reads are initiated by either a current address read or a
random address read. After the addressing master receives the data byte it responds with
an acknowledge. As long as the slave receives an acknowledge it will continue to increment
the current address register and clock out sequential data bytes.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST72345-D/RAIS | 功能描述:子卡和OEM板 8 BITS MICROCONTR RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| ST72361 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU with Flash or ROM, 10-bit ADC, 5 timers, SPI, 2x LINSCI⑩ |
| ST72361_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU with Flash or ROM, 10-bit ADC, 5 timers, SPI, 2x LINSCI⑩ |
| ST72361K6T6 | 制造商:STMicroelectronics 功能描述:ROMLESS MICRO WITH 2 UART - Bulk |
| ST72371 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH 16K ROM/OTP/EPROM,512 BYTES RAM, ADC, DAC (PWM), TIMER, I2C AND SCI |
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