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參數(shù)資料
| 型號(hào)： | ST7036-0A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dot Matrix LCD Controller/Driver |
| 中文描述： | 點(diǎn)陣LCD控制器/驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 17/72頁 |
| 文件大?。?/td> | 864K |
| 代理商： | ST7036-0A |
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ST7036
V1.1
2003/12/24
17/72
During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON
RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is
done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.
The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS bit input in IIC interface.
Table 2. Various kinds of operations according to RS and R/W bits.
z
When BF = "High”, it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not High.
z
Address Counter (AC)
Address Counter(AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
Busy Flag (BF)
RS R/W
L
H
Operation
L
L
Instruction Write operation (MPU writes Instruction code into IR)
Data Write operation (MPU writes data into DR)
S 0 1 1 1 1
1
R
S
0 A
control byte
A
data byte
Co
0
R
S
A
control byte
A
data byte
A P
Co
slave address
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
2n>=0 bytes
command word
n>=0 bytes
MSB.......................LSB
1 byte
R/W
Write mode
C
o
R
S
0 0 0 0 0 0
control byte
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
data byte
1 0
0 1 1 1 1
R
/
W
1 0
slave address
Fig .5 IIC Interface protocol
0
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
Another control byte will follow the data byte unless a STOP condition is received.
Co
1
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