參數(shù)資料
型號(hào)： ST6397
廠商： 意法半導(dǎo)體
英文描述： 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD
中文描述： 8位微控制器HCMOS電視頻率合成帶OSD
文件頁(yè)數(shù)： 36/68頁(yè)
文件大?。?/td> 560K
代理商： ST6397
HWDR
Hardware Activated Watchdog Register
(D8h, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
C = Watchdog ActivationBit
SR = SoftwareReset Bit
T1-T6 = Counter Bits
Figure39. Watchdog Register
HARDWARE ACTIVATED DIGITAL WATCHDOG
FUNCTION
(Continued)
T1-T6.
These are the watchdog counter bits. It
should be noted that D7 (T1) is the LSB of the
counter and D2 (T6) is the MSB of the counter,
these bits are in the opposite orderto normal.
SR.
This bit is set to one during the reset phase
and will generate a software reset if cleared to
zero.
C.
This is the watchdog activation bit that is hard-
ware set. The watchdog function is always acti-
vated independentlyofchangesof valueof this bit.
The register reset value is FEh (Bit 1-7 setto one,
Bit 0cleared).
SERIAL PERIPHERALINTERFACE
The ST639x Serial Peripheral Interface (SPI) has
been designed to be cost effective and flexible in
interfacing the various peripherals in TV applica-
tions.
It maintains the software flexibility but adds hard-
ware configurationssuitable todrivedeviceswhich
require a fast exchange of data. The three pins
dedicated for serial data transfer (single master
only) can operate in the followingways:
- asstandard I/Olines (software configuration)
- asS-BUS or as I
2
CBUS(two pins)
- asstandard (shift register) SPI
When usingthe hardwareSPI,a fixed clockrate of
62.5kHz is provided.
It has to be noted that the firstbit that is output on
the data line bythe 8-bit shiftregisteris the MSB.
SPI Data/Control Registers
For I/O details on SCL (Serial Clock), SDA (Serial
Data) and SEN (Serial Enable) please refer to I/O
Ports description with reference to the following
registers:
PortC data register,AddressC2h (Read/Write).
- BITD0 “SCL”
- BITD1 “SDA”
- BITD3 “SEN”
Port C data direction register, Address C6h
(Read/Write).
SSDR
SPI Serial Data Register
(CCh, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7 = Data Bits
Figure 40. SPI Serial Data Register
D7-D0.
These are the SPI data bits. They can be
neither read nor written when SPI is operating
(BUSY bitset).They are undefinedafter reset.
ST6391,92,93,95,97,99
32/64
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