參數(shù)資料
型號: ST6397
廠商: 意法半導(dǎo)體
英文描述: 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD
中文描述: 8位微控制器HCMOS電視頻率合成帶OSD
文件頁數(shù): 32/68頁
文件大?。?/td> 560K
代理商: ST6397
TIMERS
TheST639xdevices offertwo on-chipTimer periph-
erals consisting of an 8-bit counterwith a 7-bitpro-
grammableprescaler, thusgiving amaximum count
of 2
15
,and a controllogic thatallows configuringthe
peripheral operating mode. Figure 32 shows the
timer blockdiagram.The contentof the 8-bitcount-
ers can be read/written in the Timer/Counter regis-
tersTCR thatcanbeaddressedinthedataspaceas
RAMlocation at addressesD3h (Timer 1) and DBh
(Timer 2). The state of the 7-bit prescaler can be
readin thePSCregisterat addressesD2h (Timer1)
andDAh (Timer 2). Thecontrollogic is managedby
TSCR registersat D4h (Timer 1) and DCh (Timer 2)
addressesasdescribedin thefollowingparagraphs.
The following description applies to both Timer 1
and Timer2. The 8-bitcounter isdecrement bythe
output (rising edge) coming from the 7-bit pres-
caler and can be loaded and read under program
control. When it decrements to zero then the TMZ
(timer zero)bit in the TSCR is set to one. Ifthe ETI
(enable timer interrupt) bit in the TSCR is also set
to one an interrupt request, associatedto interrupt
vector #3 (forTimer1) and #1 for Timer2, isgener-
ated. The interruptof the timer can be usedto exit
the MCUfrom the WAIT mode.
The prescaler decrements on rising edge. The
prescaler input is the oscillator frequency divided
by 12.
Depending on the division factor programmed by
PS2/PS1/PS0(see Table 9) bits in the TSCR, the
clock input of the timer/counter register is multi-
plexed to differentsources.
Ondivision factor1, theclockinputoftheprescaleris
alsothatoftimer/counter;onfactor2,bit0ofprescaler
registerisconnectedtotheclockinputof TCR.
This bitchanges its statewith the halffrequencyof
prescaler clock input. On factor 4, bit 1 of PSC is
connectedto clockinput of TCR, and so on. Ondi-
vision factor 128, the MSB bit 6 of PSC is con-
nected to clock input of TCR. The prescaler
initialize bit (PSI)in the TSCR register mustbe set
to one to allow the prescaler (and hence the
counter) to start. If it is cleared to zero then all of
the prescalerbits are setto one and the counter is
inhibited fromcounting.
The prescaler can be given any value between 0
and 7Fh by writing to the relatedregister address,
if bitPSIin theTSCR register isset to one.The tap
of theprescaleris selectedusingthePS2/PS1/PS0
bits in the control register. Figure 33 shows the
timer working principle.
Figure32. Timer Peripheral Block Diagram
ST6391,92,93,95,97,99
28/64
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