參數(shù)資料
型號: ST62T03C
廠商: 意法半導(dǎo)體
英文描述: 8-Bit OTP MCUs with A/D Converter, Oscillator Safeguard, Safe Reset and 16 Pins(8位OTP微處理器(8M))
中文描述: 8位微控制器與檢察官辦公室的A / D轉(zhuǎn)換器,振蕩器保障,安全復(fù)位和16引腳(8位檢察官辦公室微處理器(8米))
文件頁數(shù): 28/70頁
文件大?。?/td> 747K
代理商: ST62T03C
28/70
ST62T00C/T01C ST62T03C/E01C
INTERRUPTS
(Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused
Bit 6 =
LES
:
Level/Edge Selection bit
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 =
ESB
: Edge Selection bit
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 =
GEN
: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt Sources
Interrupt sources available on the ST62E01C/
T01C are summarized in the
Table 8
with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Table 8. Interrupt Requests and Mask Bits
*Except ST62T03C
7
0
-
LES
ESB
GEN
-
-
-
-
Peripheral
Register
Address
Register
Mask bit
Masked Interrupt Source
Interrupt
vector
GENERAL
IOR
C8h
GEN
All Interrupts, excluding
NM
I
TMZ: TIMER Overflow
EOC: End of Conversion
PAn pin
PBn pin
TIMER
A/D CONVERTER(*)
Port PAn
Port PBn
TSCR
ADCR
ORPA-DRPA
ORPB-DRPB
D4h
D1h
C4h-CCh
C5h-CDh
ETI
EAI
ORPAn-DRPAn
ORPBn-DRPBn
Vector 3
Vector 4
Vector 1
Vector 2
44
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