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參數(shù)資料
| 型號(hào)： | ST62P08CM1 |
| 英文描述： | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTROM. EPROM. A/D CONVERTER. OSCILLATOR SAFEGUARD. SAFE RESET AND 20 PINS |
| 中文描述： | 8位微控制器（MCU）的與檢察官辦公室。光盤。 FASTROM。存儲(chǔ)器。的A / D轉(zhuǎn)換器。振蕩器保障。安全復(fù)位和20圖釘 |
| 文件頁(yè)數(shù)： | 44/84頁(yè) |
| 文件大小： | 918K |
| 代理商： | ST62P08CM1 |
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ST62T53C/T60C/T63C ST62E60C
TIMER
(Cont’d)
4.2.1 Timer Operation
The Timer prescaler is clocked by the prescaler
clock input (f
INT
÷ 12).
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high.
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request associated with Interrupt Vector
#4 is generated. When the counter decrements to
zero, the TMZ bit in the TSCR register is set to
one.
4.2.3 Application Notes
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
Figure 27. Timer Working Principle
BIT0
BIT1
BIT2
BIT3
BIT6
BIT5
BIT4
CLOCK
7-BIT PRESCALER
8-1 MULTIPLEXER
8-BIT COUNTER
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
1
0
2
3
4
5
6
7
PS0
PS1
PS2
VA00186
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