參數(shù)資料
型號: ST62E40B
廠商: 意法半導體
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 39/72頁
文件大小: 445K
代理商: ST62E40B
39/72
39
ST62T40B/E40B
4.2 TIMER 1 & 2
The MCU features two on-chip Timer peripheral
named TIMER 1 & TIMER 2. Each of these timers
consist of an 8-bit counter with a 7-bit programma-
ble prescaler, giving a maximum count of 2
15
.
Figure 22 and Figure 23 show the Timer Block Di-
agrams. An external TIMER pin is available to the
user on the TIMER 1 allowing external control of
the counting clock or signal generation.
The content of the 8-bit counter can be read/writ-
ten in the Timer/Counter register, TCR, while the
state of the 7-bit prescaler can be read in the PSC
register. The control logic device is managed in
the TSCR register as described in the following
paragraphs.
The 8-bit counter is decremented by the output
(rising edge) coming from the 7-bit prescaler and
can be loaded and read under program control.
When it decrements to zero then the TMZ (Timer
Zero) bit in the TSCR is set to “1”. If the ETI (Ena-
ble Timer Interrupt) bit in the TSCR is also set to
“1”, an interrupt request is generated as described
in the Interrupt Chapter. The Timer interrupt can
be used to exit the MCU from WAIT mode.
The prescaler input can be either the internal fre-
quency f
INT
divided by 12 (TIMER 1 & 2) or an ex-
ternal clock applied to the TIMER pin (TIMER 1).
The prescaler decrements on the rising edge. De-
pending on the division factor programmed by
PS2, PS1 and PS0 bits in the TSCR. The clock in-
put of the timer/counter register is multiplexed to
different sources. For division factor 1, the clock
input of the prescaler is also that of timer/counter;
for factor 2, bit 0 of the prescaler register is con-
nected to the clock input of TCR. This bit changes
its state at half the frequency of theprescaler input
clock. For factor 4, bit 1 of the PSC is connected to
the clock input of TCR, and so forth. The prescaler
initialize bit, PSI, in the TSCR register must be set
to “1” to allow the prescaler (and hence the coun-
ter) to start. If it is cleared to “0”, all the prescaler
bits are set to “1” and thecounter is inhibited from
counting. The prescaler can be loaded with any
value between 0 and 7Fh, if bit PSI is set to “1”.
The prescaler tap is selected by means of the
PS2/PS1/PS0 bits in the control register.
Figure 21 illustrates the Timer’s working principle.
Figure 21. Timer Working Principle
BIT0
BIT1
BIT2
BIT3
BIT6
BIT5
BIT4
CLOCK
7-BIT PRESCALER
8-1 MULTIPLEXER
8-BIT COUNTER
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
1
0
2
3
4
5
6
7
PS0
PS1
PS2
VA00186
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