參數(shù)資料
型號： ST624XB-KIT
英文描述： STARTER KIT DATASHEET FOR ST624X
中文描述： 入門套件小冊子的ST624X
文件頁數(shù)： 54/74頁
文件大小： 733K
代理商： ST624XB-KIT
54/74
ST62T46B/E46B
POWER SUPPLY SUPERVISOR (Continued)
4.6.2 PSS Register
The PSS register permits control over the PSS de-
vice. The register can be addressed in the data
space as a RAM location at DAh. This register is
cleared after Reset.
PSS Status Control Register (PSSCR)
Address: DAh - Read/Write
Bit 7 =
PIF
. Interrupt flag bit.This bit is the interrupt
flag. This bit is set (resp. cleared) as soon as the
equality between nxV
PSS
and mxV
DD
/13 (resp.
(m+1)xV
DD
/13) occurs.
Bit 6 =
PEI
. Interrupt mask bit. This bit is the au-
thorization bit of the interrupt request: – If PEI is
set, the interrupt request can reach the Core. – If
PEI is cleared, the interrupt request cannot reach
the Core.
Bits 5-4 =
PDV1, PDV0
.
Division rate selection bit
.
The PDV1/0 bits are used to select the rate of divi-
sion
of
the
V
DD
voltage
(m+1)xV
DD
/13, according to the hysteresis).
(mxV
DD
/13
or
Table 18. V
DD
Voltage division rate selection
bits
Bits 3-1 =
PDR2, PDR1, PDR0
.
Division rate se-
lection bit.
The PDR2/1/0 bits are used to inhibit
the PSS device and to select the division rate of
the PSS voltage (nxV
PSS
/13).
Bit 0 =
D0
. The PSS comparator output is valid 8
cycle times after the programming of the PDR2/1/0
bits. It is forced to zero in the meantime.
Table 19. P
SS
Voltage division rate selection bits
PDR2
PDR1
PDR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
7
0
PIF
PEI
PDV1
PSS
PDV0
PSS
PDR2
PSS
PDR1
PSS
PDR0
PSS
D0
PDV1
0
0
1
1
PDV0
0
1
0
1
mxV
DD
/13
3xV
DD
/13
5xV
DD
/13
6xV
DD
/13
7xV
DD
/13
(m+ 1) xV
DD
/13
4xV
DD
/13
6xV
DD
/13
7xV
DD
/13
8xV
DD
/13
PSS State
IDLE
BUSY
BUSY
BUSY
BUSY
BUSY
nxV
PSS
/13
4xV
PSS
/13
5xV
PSS
/13
6xV
PSS
/13
7xV
PSS
/13
V
PSS
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