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參數(shù)資料
| 型號(hào)： | ST6225CM1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, OSCILLATOR SAFEGUARD, SAFE RESET AND 28 PINS |
| 中文描述： | 8位檢察官辦公室/存儲(chǔ)器與阿微控制器/ D轉(zhuǎn)換器，振蕩器保障，安全復(fù)位和28個(gè)引腳 |
| 文件頁(yè)數(shù)： | 5/70頁(yè) |
| 文件大?。?/td> | 472K |
| 代理商： | ST6225CM1 |
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ST62T15C/T25C/E25C
1.2 PIN DESCRIPTIONS
V
DD
and V
SS
. Power is supplied to the MCU via
these two pins. V
DD
is the power connection and
V
SS
is the ground connection.
OSCin and OSCout.
These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
RESET
. The active-low RESET pin is used to re-
start the microcontroller. Internal pull-up is provid-
ed at this pin.
TEST/V
.
The TEST must be held at V
for nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM
programming Mode is entered.
NMI.
The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive. The user can select as op-
tion the availability of an on-chip pull-up at this pin.
TIMER.
This is thetimer I/O pin. In input mode it is
connected to the prescaler and acts as external
timer clock input or as control gate input for the in-
ternal timer clock. In output mode thetimer pin out-
puts the data bit when a time-out occurs. The user
can select as option the availability of an on-chip
pull-up at this pin.
PA0-PA7.
These 8 lines are organized as one I/O
port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors,open-drain or push-pull outputs. PA0-
PA3 can also sink 20mA for direct LED driving
while PA4-PA7 can be programmed as analog in-
puts for the A/D converter.
PB0-PB7.
These 8 lines are organized as one I/O
port (B). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain orpush-pull outputs, or as
analog inputs for the A/D converter.
PC4-PC7.
These 4 lines are organized as one I/O
port (C). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain orpush-pull outputs, or as
analog inputs for the A/D converter.
Figure 2. ST62T15C,T25C and E25C Pin
Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
DD
TIMER
OSCin
OSCout
NMI
Ain/PC7
Ain/PC6
Ain/PC5
Ain/PC4
V
PP
/TEST
RESET
Ain/PB7
Ain/PB6
Ain/PB5
V
SS
PA0/20mA Sink
PA1/20mA Sink
PA2/20mA Sink
PA3/20mA Sink
PA4/Ain
PA5/Ain
PA6/Ain
PA7/Ain
PB0/Ain
PB1/Ain
PB2/Ain
PB3/Ain
PB4/Ain
28
27
26
25
24
23
22
21
5
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