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參數(shù)資料
| 型號： | ST52514K1 |
| 英文描述： | IC MAX 7000 CPLD 128 100-FBGA |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 44/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52514K1 |
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6 CLOCK, RESET & POWER SAVING MODES
6.1 Clock
The ST52F501L/F502L Clock Generator module
generates the internal clock for the internal Control
Unit, ALU and on-chip peripherals. The Clock is
designed to require a minimum of external
components.
ST52F501L/F502L devices supply the internal
oscillator in four clock modes:
s
External quartz oscillator
s
External clock
s
External RC oscillator
s
Internal oscillator
The device always starts in internal clock mode,
excluding any external clock source. After the
start-up phase the clock is configured according to
the user definition programmed in the Option Byte
0 (OSC_CR). The internal clock generator can
supply an internal clock signal with a fixed
frequency of 10 MHz ± 1%, without the need for
external components. In order to obtain the
maximum
accuracy,
the
frequency
can
be
calibrated by configuring the related Option byte 2
(OSC_SET). The internal clock can be divided by
the configurable prescaler, set with the OSC_SET
Option byte, by a factor 2, 4 or 8 thus obtaining 5
MHz, 2.5 MHZ and 1.25 MHZ clock frequency.
The external oscillator mode uses a quartz crystal
or a ceramic resonator connected to OSCin and
OSCout as illustrated in Figure 6.1. This figure also
illustrates the connection of an external clock.
The ST52F501L/F502L oscillator circuit generates
an internal clock signal with the same period and
phase as the OSCIN input pin. The maximum
frequency allowed is 24 MHz.
When the external oscillator is used, the loop gain
can be adapted to the various frequencies values
by configuring the three bits of the Option Byte 1
CLK_SET (see Register Description, Table 6.2).
Figure 6.1 Oscillator Connections
When an external clock is used, it must be
connected to the pin OSCIN while OSCOUT can
be floating. In this case, Option Byte 1 bits must be
written with 0 (000).
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
Rs),
oscillator
load
capacitance
(CL),
IC
parameters, environment temperature and supply
voltage.
The
crystal
or
ceramic
leads
and
circuit
connections must be as short as possible. Typical
values for CL1, CL2 are 10pF for a 20 MHz crystal.
The clock signal can also be generated by an
external RC circuit offering additional cost savings.
Figure 6.1 illustrates the possible connections.
Frequency is a function of resistor, capacitance,
supply voltage and operating temperature; some
indicative values when Vdd=1.8V and T=25°, are
shown in Table 6.1.
The clock signal generates two internal clock
signals: one for the CPU and one for the
peripherals. The CPU clock frequency can be
reduced, in order to decrease current conception,
by setting the CPU_CLK Configuration Register 46
(02Eh). The CPU clock can be reduced up to 64
times (see Register Description).
OSCin
OSCout
ST FIVE
OSCin
ST FIVE
OSCout
CRYSTAL CLOCK
EXTERNAL CLOCK
Cl1
10pF
Cl2
10pF
CLOCK
INPUT
OSCin
ST FIVE
OSCout
RC CIRCUIT CLOCK
Vdd
Vss
RC
Table 6.1 RC Osc. indicative freq. (Vdd=1.8V)
C (pF)
R(K
)
fosc (KHz)
Variation
10
3.3
6000
± 3%
10
2500
± 3%
100
300
± 3%
20
3.3
4000
± 3%
10
1500
± 3%
100
187
± 5.5%
50
3.3
2350
± 18%
10
914
± 18%
100
130
± 20%
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