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參數(shù)資料
| 型號(hào)： | ST52513Y2 |
| 英文描述： | MAX 3000A CPLD 256 MC 256-FBGA |
| 中文描述： | 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 56/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513Y2 |
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Example 1:
IF Input1 IS NOT Mbf1 AND Input4 is Mbf12 OR Input3 IS Mbf8 THEN Crisp1
is codified by the following instructions:
Example 2, the priority of the operator is fixed by the brackets:
IF (Input3 IS Mbf1 AND Input4 IS NOT Mbf15) OR (Input1 IS Mbf6 OR Input6 IS NOT Mbf14) THEN Crisp2
At the end of the fuzzy rules related to the current Fuzzy Variable, by using the instruction OUT
reg, the
specified register is written with the computed value. Afterwards, the control of the algorithm returns to the
CU. The next Fuzzy Variable evaluation must start again with a FUZZY instruction.
ISNOT 1 1 calculates the NOT α value of Input1 with Mbf1 and stores the result in internal registers
FZAND
implements the operation AND between the previous and the next alpha value evaluated
IS 4 12
fixes the
α value of Input
4 with Mbf12 and stores the result in internal registers
FZOR
implements the operation OR between the previous and the next alpha value evaluated
IS 3 8
fixes the
α value of Input
3 with Mbf8 and stores the result in internal registers
CON
crisp1 multiplies the result of the last operation with the crisp value crisp1
(
parenthesis open to change the priority
IS 3 1
fixes the
α value of Input
3 with Mbf1 and stores the result in internal registers
FZAND
implements the operation AND between the previous and the next alpha value evaluated
ISNOT 4 15 calculates the NOT α value of Input4 with Mbf15 and stores the result in internal registers
)
parenthesis closed
FZOR
implements the operation OR between the previous and the next alpha value evaluated
(
parenthesis open to change the priority
IS 1 6
fixes the
α value of Input
1 with Mbf6 and stores the result in internal registers
FZOR
implements the operation OR between the previous and the next alpha value evaluated
ISNOT 2 14 calculates the NOT
α value of Input
6 with Mbf14 and stores the result in internal registers
)
parenthesis closed
CON
crisp2 multiplies the result of the last operation with the crisp value crisp2
相關(guān)PDF資料 |
PDF描述 |
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| ST52513Y3 | MAX II CPLD 570 LE 256-FBGA |
| ST52514F1 | MAX II CPLD 570 LE 100-TQFP |
| ST52514F3 | IC MAX 7000 CPLD 128 100-TQFP |
| ST52514G1 | IC MAX 7000 CPLD 32 44-TQFP |
| ST52514G3 | IC MAX 7000 CPLD 64 100-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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