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參數(shù)資料
| 型號(hào)： | ST52513Y2 |
| 英文描述： | MAX 3000A CPLD 256 MC 256-FBGA |
| 中文描述： | 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 26/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513Y2 |
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Figure 3.2 Data Processing Unit (DPU)
The
DPU
receives,
stores
and
sends
the
instructions
deriving
from
the
Program/Data
Memory, Register File or from the peripherals. It is
controlled by the CU on the basis of the decoded
instruction. The Fuzzy registers store the partial
results of the fuzzy computation. The accumulator
register is used by the ALU and is not accessible
directly: the instructions used by the ALU can
address
all
the
Register
File
locations
as
operands, allowing a more compact code and a
faster execution.
The following addressing modes are available:
inherent, immediate, direct, indirect, bit direct.
3.1.1 Program Counter.
The Program Counter (PC) is a 16-bit register that
contains the address of the next memory location
to be processed by the core. This memory location
may be both an instruction or data address.
The Program Counter’s 16-bit length allows the
direct addressing of a maximum of 64 Kbytes in the
Program/Data Memory space.
The PC can be changed in the following ways:
s
JP (Jump)
PC = Jump Address
s
Interrupt
PC = Interrupt Vector
s
RETI
PC = Pop (stack)
s
RET
PC = Pop (stack)
s
CALL
PC = Subroutines address
s
Reset
PC = Reset Vector
s
Normal Instruction
PC = PC + 1
3.1.2 Flags.
The ST FIVE core includes different sets of flags
that correspond to 2 different modes: normal mode
and interrupt mode. Each set of flags consist of a
CARRY flag (C), ZERO flag (Z) and SIGN flag (S).
Each set is stacked: one set of flags is used during
normal operation and other sets are used during
each level of interrupt. Formally, the user has to
manage only one set of flags: C, Z and S since the
flag stack operation is performed automatically.
PROGRAM COUNTER
REGISTER
FILE
256 Bytes
REGISTER FILE
ADDRESS
ACCUMULATOR
DECISION
REGISTERS
ALU
FLAGS REG.
Memory Address
Peripherals
Control Unit
Program Memory
Input Registers
Peripherals
Interrupts Unit
PROCESSOR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52513Y3 | MAX II CPLD 570 LE 256-FBGA |
| ST52514F1 | MAX II CPLD 570 LE 100-TQFP |
| ST52514F3 | IC MAX 7000 CPLD 128 100-TQFP |
| ST52514G1 | IC MAX 7000 CPLD 32 44-TQFP |
| ST52514G3 | IC MAX 7000 CPLD 64 100-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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