參數(shù)資料
型號(hào)： ST52513F3
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： MICROCONTROLLER, PDSO20
封裝： ROHS COMPLIANT, SOP-20
文件頁(yè)數(shù)： 26/136頁(yè)
文件大?。?/td> 2791K
代理商： ST52513F3
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16.12.4 Static and Dynamic Latch-up.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed on
each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard.
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 16.10.
Figure 16.10 Simplified Diagram of the ESD Generator for DLU
Notes:
1. Class description: Class A is an STMicroelectronics internal specification. All its limits are higher than
the JEDEC specification, that means when a device belongs to Class A it exceeds the JEDEC standard.
Class B strictly covers all the JEDEC criteria (international standard).
16.12.5 ESD Pin Protection Strategy. In order
to protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit
elements. Stress generally affects the circuit
elements, which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements that are to
be protected must not receive excessive current,
voltage, or heating within their structure.
An ESD network combines the different input and
output protections. This network works by allowing
safe discharge paths for the pins subject to ESD
stress. Two critical ESD stress cases are
presented in Figure 16.11 and Figure 16.12 for
standard pins.
Standard Pin Protection
In order to protect the output structure the following
elements are added:
- A diode to VDD (3a) and a diode from VSS (3b)
- A protection device between VDD and VSS (4)
In order protect the input structure the following
elements are added:
- A resistor in series with pad (1)
- A diode to VDD (2a) and a diode from VSS (2b)
- A protection device between VDD and VSS (4)
Symbol
Parameter
Conditions
Class 1)
LU
Static latch-up class
TA=25° C
TA=85° C
A
DLU
Dynamic latch-up class
VDD=5.5V, fOSC= 8 MHz, TA=25° C
A
ST FIVE
V
DD
V
SS
DISCHARGE TIP
HV RELAY
DISCHARGE
RETURN CONNECTION
ESD
GENERATOR
R
D= 330 Ω
R
CH= 50 MΩ
C
S= 150 pF
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