參數(shù)資料
型號(hào)： ST52513F3
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PDSO20
封裝： ROHS COMPLIANT, SOP-20
文件頁數(shù)： 131/136頁
文件大?。?/td> 2791K
代理商： ST52513F3
14.5 Register Description
In the following sections describe the registers
used by the I2C Interface are described.
14.5.1 I2C Interface Configuration Registers.
I2C Control Register (I2C_CR)
Configuration Register 16 (010h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used. They must be held to 0.
Bit 5: PE Peripheral Enable.
This bit is set and cleared by software
0: peripheral disabled
1: peripheral enabled
Notes:
– When PE=0, all the bits of the I2C_CR register
and the SR register except the Stop bit are reset.
All outputs are released while PE=0
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– To enable the I2C interface, write the I2C_CR
register TWICE with PE=1 as the first write only
activates the interface (only PE is set).
Bit 4: ENGC Enable General Call
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0)
.
0: General Call disabled
1: General Call enabled
Note: The
00h General
Call address is
acknowledged (01h ignored).
Bit 3: START Generation of a Start Condition
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if
ITE=1).
– In Master Mode
0: No Start generation
1: Repeated Start generation
– In Slave Mode
0: No Start generation
1: Start generation when the bus is free
Bit 2: ACK Acknowledge enable
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0)
.
0: No acknowledge returned
1: Acknowledge returned after an address
byte or a data byte is received
Bit 1: STOP Generation of a Stop Condition
This bit is set and cleared by software. It is
also cleared by hardware in master mode.
Note: This bit is not cleared when the
interface is disabled (PE=0).
– In Master Mode
0: No Stop generation
1: Stop generation after the current byte
transfer or after the current Start condition
is sent. The STOP bit is cleared by
hardware when the Stop condition is sent.
– In Slave Mode
0: No actions performed
1: Release the SCL and SDA lines after the
last
byte
transfer
(BTF=1)
in
slave
transmitter mode. In this mode the STOP
bit has to be cleared by software.
Bit 0: ITE Interrupt Enable
0: Interrupt disabled
1: Interrupt enabled
I2C Clock Control Register (I2C_CCR)
Configuration Register 17 (011h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: FM/SM Fast/Standard I2C Mode.
This bit is set and cleared by software. It is
not cleared when the interface is disabled
(PE=0).
70
-
PE
ENGC
START
ACK
STOP
ITE
70
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
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