參數(shù)資料
型號(hào)： ST24W02B6
廠商： 意法半導(dǎo)體
英文描述： Cyclone II FPGA 70K FBGA-896
中文描述： I2C串行EEPROM的
文件頁(yè)數(shù)： 4/16頁(yè)
文件大小： 145K
代理商： ST24W02B6
AI01100
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
200
300
400
0
4
8
12
16
20
CBUS (pF)
R
)
VCC = 5V
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION
I
2
C Bus Background
The ST24/25x02 support the I
2
C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x02 are always slave
devices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x02 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x02
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input.
During data input the ST24/25x02
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing.
To start communication be-
tween the bus master and the slave ST24/25x02,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
SIGNAL DESCRIPTIONS
(cont’d)
4/16
ST24/25C02, ST24C02R, ST24/25W02
相關(guān)PDF資料
PDF描述
ST24W02M1 Cyclone II FPGA 5K TQFP-144
ST24W02M3 FPGA, FLEX 10K, 20K GATES, TQFP144; Logic IC family:FPGA; Logic IC Base Number:10; Logic IC function:EPF10K20; Voltage, supply:5.0V; Case style:TQFP; Gates, No. of:20000; I/O lines, No. of:102; Pins, No. of:144; Temp, op. RoHS Compliant: Yes
ST24W02M6 CPLD. MAX 7000, 160 MACROCELLS, TQFP100; Logic IC family:CPLD (EPLD); Logic IC Base Number:7160; Logic IC function:EPM7160S; Voltage, supply:5V; Case style:TQFP; Gates, No. of:3200; I/O lines, No. of:84; Macrocells, No. of:160; Pins, RoHS Compliant: Yes
ST24C02M3TR SERIAL 2K (256 x 8) EEPROM
ST25C02M3TR SERIAL 2K (256 x 8) EEPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST24W02B6TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM
ST24W02CB1 功能描述:電可擦除可編程只讀存儲(chǔ)器 5.5V 2K (256x8) RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
ST24W02M1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C Serial EEPROM
ST24W02M1TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM
ST24W02M3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C Serial EEPROM
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