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參數(shù)資料
| 型號： | ST24W02B6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Cyclone II FPGA 70K FBGA-896 |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 145K |
| 代理商： | ST24W02B6 |
Mode
RW bit
MODE
Bytes
Initial Sequence
Current Address Read
’1’
X
1
START, Device Select, RW = ’1’
Random Address Read
’0’
X
1
START, Device Select, RW = ’0’, Address,
’1’
reSTART, Device Select, RW = ’1’
Sequential Read
’1’
X
1 to 256
Similar to Current or Random Mode
Byte Write
’0’
X
1
START, Device Select, RW = ’0’
Multibyte Write
(2)
’0’
V
IH
4
START, Device Select, RW = ’0’
Page Write
’0’
V
IL
8
START, Device Select, RW = ’0’
Notes:
1. X = V
or V
2. Multibyte Write not available in ST24/25W02 versions.
Table 4. Operating Modes
(1)
Device Code
Chip Enable
RW
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Device Select
1
0
1
0
E2
E1
E0
RW
Note:
The MSB b7 is sent first.
Table 3. Device Select Code
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: V
CC
lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
CC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL).
The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 3).
Serial Data (SDA).
The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
CC
to act as pull up (see Figure 3).
Chip Enable (E2 - E0).
These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or tied to V
CC
or V
SS
to
establish the device select code.
Mode (MODE).
The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at V
IL
or V
IH
for the Byte Write
mode, V
IH
for Multibyte Write mode or V
IL
for Page
Write mode. When unconnected, the MODE input
is internally read as a V
IH
(Multibyte Write mode).
Write Control (WC).
An hardware Write Control
feature (WC) is offered only for ST24W02 and
ST25W02 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = V
IH
) or disable (WC =
V
IL
) the internal write protection. When uncon-
nected, the WC input is internally read as V
IL
and
the memory area is not write protected.
3/16
ST24/25C02, ST24C02R, ST24/25W02
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST24W02M1 | Cyclone II FPGA 5K TQFP-144 |
| ST24W02M3 | FPGA, FLEX 10K, 20K GATES, TQFP144; Logic IC family:FPGA; Logic IC Base Number:10; Logic IC function:EPF10K20; Voltage, supply:5.0V; Case style:TQFP; Gates, No. of:20000; I/O lines, No. of:102; Pins, No. of:144; Temp, op. RoHS Compliant: Yes |
| ST24W02M6 | CPLD. MAX 7000, 160 MACROCELLS, TQFP100; Logic IC family:CPLD (EPLD); Logic IC Base Number:7160; Logic IC function:EPM7160S; Voltage, supply:5V; Case style:TQFP; Gates, No. of:3200; I/O lines, No. of:84; Macrocells, No. of:160; Pins, RoHS Compliant: Yes |
| ST24C02M3TR | SERIAL 2K (256 x 8) EEPROM |
| ST25C02M3TR | SERIAL 2K (256 x 8) EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST24W02B6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM |
| ST24W02CB1 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 5.5V 2K (256x8) RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| ST24W02M1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C Serial EEPROM |
| ST24W02M1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL 2K (256 x 8) EEPROM |
| ST24W02M3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C Serial EEPROM |
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