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參數(shù)資料
| 型號： | ST24LW21M6TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| 中文描述： | 1千位x8雙模式串行EEPROM的韋莎插頭 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 159K |
| 代理商： | ST24LW21M6TR |
Symbol
Alt
Parameter
Min
Max
Unit
t
CH1CH2
t
R
Clock Rise Time
1
μ
s
t
CL1CL2
t
F
Clock Fall Time
300
ns
t
DH1DH2
t
R
Input Rise Time
1
μ
s
t
DL1DL1
t
F
Input Fall Time
300
ns
t
CHDX (1)
t
SU:STA
Clock High to Input Transition
4.7
μ
s
t
CHCL
t
HIGH
Clock Pulse Width High
4
μ
s
t
DLCL
t
HD:STA
Input Low to Clock Low (START)
4
μ
s
t
CLDX
t
HD:DAT
Clock Low to Input Transition
0
μ
s
t
CLCH
t
LOW
Clock Pulse Width Low
4.7
μ
s
t
DXCX
t
SU:DAT
Input Transition to Clock Transition
250
ns
t
CHDH
t
SU:STO
Clock High to Input High (STOP)
4.7
μ
s
t
DHDL
t
BUF
Input High to Input Low (Bus Free)
4.7
μ
s
t
CLQV (2)
t
AA
Clock Low to Next Data Out Valid
0.2
3.5
μ
s
t
CLQX
t
DH
Data Out Hold Time
200
ns
f
C
f
SCL
Clock Frequency
100
kHz
t
W
t
WR
Write Time
10
ms
Notes:
1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
Table 8. AC Characteristics, I
2
C Bidirectional Mode for Clock Frequency = 100kHz
(T
A
= –40 to 85
°
C; V
CC
= 3.6V to 5.5V)
Symbol
Alt
Parameter
Min
Max
Unit
t
VCHQX
t
VAA
Output Valid from VCLK
500
ns
t
VCHVCL
t
VHIGH
VCLK High Time
600
ns
t
VCLVCH
t
VLOW
VCLK Low Time
1.3
μ
s
t
CLQZ
t
VHZ
Mode Tansition Time
500
ns
t
VPU(1,2)
Transmit-only Power-up Time
0
ns
t
VH1VH2
(2)
t
R
VCLK Rise Time
1
μ
s
t
VL1VL2
(2)
t
F
VCLK Fall Time
1
μ
s
t
RECOVERY (2)
Recovery Time
1.5
3.5
sec
Notes:
1. Refer to Figure 3.
2. Sampled only, not 100% tested.
Table 9. AC Characteristics, Transmit-only Mode
(T
A
= –40 to 85
°
C; V
CC
= 3.6V to 5.5V)
11/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
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