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參數(shù)資料
| 型號： | ST24LC21B1TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Controller IC; Package/Case:14-DIP; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No; Mounting Type:Through Hole |
| 中文描述： | 1kB的x8串行EEPROM的雙模式為韋莎插頭 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 149K |
| 代理商： | ST24LC21B1TR |
After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
W
) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master. The sequence is as follows:
– Initial condition: a Write is in progress (see Figure
9).
– Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of the
new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it will respond
with an ACK, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction was already sent
during Step 1).
WRITE Cycle
in Progress
AI01099B
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
Send
Byte Address
First byte of instruction
with RW = 0 already
decoded by ST24xxx
Figure 9. Write Cycle Polling using ACK
DEVICE OPERATIONS
(cont’d)
11/18
ST24LC21
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST24LC21BB1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| ST24LC21BB1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24LC21BB6 | 功能描述:電可擦除可編程只讀存儲器 Dual Mode 1K (128x8) RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| ST24LC21BB6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY |
| ST24LC21BM1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
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