- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380693 > ST24E16M1 (意法半導(dǎo)體) Cyclone II FPGA 70K FBGA-672 PDF資料下載
參數(shù)資料
| 型號： | ST24E16M1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Cyclone II FPGA 70K FBGA-672 |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 118K |
| 代理商： | ST24E16M1 |
AI01115
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
25
50
75
100
0
4
8
12
16
20
CBUS (pF)
R
)
VCC = 5V
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus, f
C
= 400kHz
DEVICE OPERATION
I
2
C Bus Background
The ST24/25E16 support the extended addressing
I
2
C protocol. This protocol defines any device that
sends data onto the bus as a transmitter and any
device that reads the data as a receiver.The device
that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The ST24/25E16
are always slave devices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25E16 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25E16
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse the receiver pulls the SDA bus low
to acknowledge the receipt of the 8 bits of data.
Data Input.
During data input the ST24/25E16
sample the SDA bus signal on the rising edge of
the clock SCL. For correct device operation the
SDA signal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL line is low.
Device Selection.
To start communication be-
tween the bus master and the slave ST24/25E16,
the master must initiate a START condition. The 8
bits sent after a START condition are made up of a
device select of 4 bits that identifies the device type,
3 Chip Enable bits and one bit for a READ (RW =
1) or WRITE (RW = 0) operation. There are two
modes both for read and write. These are summa-
rised in Table 4 and described hereafter. A commu-
nication between the master and the slave is ended
with a STOP condition.
4/16
ST24E16, ST25E16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST24E16M1TR | IC MAX 7000 CPLD 128 100-PQFP |
| ST24E16M6 | IC APEX 20KE FPGA 100K |
| ST24E16M6TR | CONFIGURATION DEVICE, 16MBIT,UBGA88; Memory type:Configuration FLASH; Interface type:Serial, Parallel; Memory size:16Mbit; Memory configuration:2MB; Time, access:90ns; Frequency:66.7MHz; Temp, op. min:0(degree C); Temp, op. RoHS Compliant: Yes |
| ST24EM1TR | 16 Kbit Serial I2C EEPROM with Extended Addressing |
| ST24EM3TR | 16 Kbit Serial I2C EEPROM with Extended Addressing |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST24E16M1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:I2C Serial EEPROM |
| ST24E16M6 | 制造商:STMicroelectronics 功能描述: |
| ST24E16M6TR | 功能描述:電可擦除可編程只讀存儲器 5.5V 16K (2Kx8) RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| ST24E256B1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| ST24E256B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。