參數(shù)資料
型號(hào): ST24E16M1
廠商: 意法半導(dǎo)體
英文描述: Cyclone II FPGA 70K FBGA-672
中文描述: I2C串行EEPROM的
文件頁數(shù): 11/16頁
文件大小: 118K
代理商: ST24E16M1
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01106B
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
R/W
ACK
ACK
ACK
ACK
ACK
ACK
ACK
R/W
ACK
ACK
Figure 9. Write Modes Sequence with Write Control = 1
sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll-over’ and the memory will continue
to output data.
Acknowledge in Read Mode.
In all read modes
the ST24/25E16 wait for an acknowledge during
the 9th bit time. If the master does not pull the SDA
line low during this time, the ST24/25E16 terminate
the data transfer and switch to a standby state.
11/16
ST24E16, ST25E16
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