參數(shù)資料
型號: ST16C552ACJ68TR-F
廠商: Exar Corporation
文件頁數(shù): 8/39頁
文件大小: 0K
描述: IC UART FIFO 16B DUAL 68PLCC
標(biāo)準(zhǔn)包裝: 250
特點: *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: 打印機
電源電壓: 2.97 V ~ 5.5 V
帶并行端口:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 帶卷 (TR)
16
ST16C552/552A
Rev. 3.40
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the eighteen 552/552A internal registers. The
assigned bit functions are more fully defined in the following paragraphs.
Table 7, ST16C552/552A INTERNAL REGISTERS
A2 A1 A0
Register
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
[Default]
Note 5*
General Register Set: Note 1*
0
RHR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
THR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
1
IER [00]
0
En
0
Modem
Receive
Transmit
Receive
Pwr
Status
Line
Holding
down
Interrupt
Status
Register
mode
interrupt
0
1
0
FCR [00]
RCVR
0
DMA
XMIT
RCVR
FIFO
trigger
mode
FIFO
enable
(MSB)
(LSB)
select
reset
0
1
0
ISR [01]
FIFO’s
0
INT
enabled
priority
status
bit-2
bit-1
bit-0
0
1
LCR [00]
divisor
set
even
parity
stop
word
latch
break
parity
enable
bits
length
enable
bit-1
bit-0
1
0
MCR [00]
Pwr
0
loop
INT A/B
[X]
-RTS
-DTR
down
back
enable
1
0
1
LSR [60]
FIFO
THR &
THR.
break
framing
parity
overrun
receive
data
TSR
empty
interrupt
error
data
error
empty
ready
1
0
MSR [X0]
CD
RI
DSR
CTS
delta
-CD
-RI
-DSR
-CTS
1
SPR [FF]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
Special Register Set: Note *2
0
DLL [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
1
DLM [XX]
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
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