參數(shù)資料
型號: ST16C550CP40
廠商: Exar Corporation
文件頁數(shù): 30/35頁
文件大?。?/td> 0K
描述: IC UART FIFO 16BYTE 40PDIP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 9
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
電源電壓: 2.97 V ~ 5.5 V
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應商設備封裝: 40-PDIP
包裝: 管件
其它名稱: 1016-1422
ST16C550
4
Rev. 5.01
Symbol
Pin
Signal
Pin Description
40
44
48
type
SYMBOL DESCRIPTION
A0
28
31
28
I
Address-0 Select Bit Internal registers address selection.
A1
27
30
27
I
Address-1 Select Bit Internal registers address selection.
A2
26
29
26
I
Address-2 Select Bit Internal registers address selection.
IOR
22
25
20
I
Read data strobe. Its function is the same as -IOR (see -
IOR), except it is active high. Either an active -IOR or IOR
is required to transfer data from 16C550 to CPU during a
read operation. Connect to logic 0 when using -IOR.
CS0
12
14
9
I
Chip Select-0. Logical 1 on this pin provides the chip select-
0 function. Connect CS0 to logic 1 if using CS1 or -CS2.
CS1
13
15
10
I
Chip Select-1. Logical 1 on this pin provides the chip select-
1 function. Connect CS1 to logic 1 if using CS0 or -CS2.
-CS2
14
16
11
I
Chip Select -2. Logical 0 on this pin provides the chip select-
2 function. Connect to logic 0 if using CS0 or CS1.
IOW
19
21
17
I
Write data strobe. Its function is the same as -IOW (see -
IOW), but it acts as an active high input signal. Either -IOW
or IOW is required to transfer data from the CPU to
ST16C550 during a write operation. Connect to logic 0 when
using -IOW.
-AS
25
28
24
I
Address Strobe. A logic 1 transition on -AS latches the state
of the chip selects and the register select bits, A0-A2. This
input is used when address and chip selects are not stable
for the duration of a read or write operation, i.e., a micropro-
cessor that needs to de-multiplex the address and data bits.
If not required, the -AS input can be permanently tied to a
logic 0.
D0-D7
1-8
2-9
43-47
2-4
I/O
Data Bus (Bi-directional) - These pins are the eight bit, tri-
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
GND
20
22
18
Pwr
Signal and Power Ground.
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