參數(shù)資料
型號: ST16C452IJ68PS-F
廠商: Exar Corporation
文件頁數(shù): 25/30頁
文件大?。?/td> 0K
描述: IC UART W/PAR PORT DUAL 68PLCC
標準包裝: 19
特點: *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié)
規(guī)程: 打印機
電源電壓: 2.97 V ~ 5.5 V
帶并行端口:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 管件
4
ST16C452/452PS
Rev. 3.20
SYMBOL DESCRIPTION
Symbol
Pin
Signal Type
Pin Description
-ERROR
63
I
Error, Printer (with internal pull-up) - General purpose input
or line printer error. This pin may be connected to the active
low (logic 0) output of a printer to indicate an error condition.
GND
2,7,54
Pwr
Signal and Power Ground.
27
INIT
57
I/O
Initialize (open drain, with internal pull-up) - General pur-
pose I/O signal. This pin may be connected for initialization
service of a connected line printer. Generally when this
signal is a logic 0, any connected printer will be initialized.
INT A/B
45,60
O
Interrupt output A/B ( three state active high) - These pins
provide individual channel interrupts, INT A-B. INT A-B are
enabled when MCR bit-3 is set to a logic 1, interrupts are
enabled in the interrupt enable register (IER), and when an
interrupt condition exists. Interrupt conditions include: re-
ceiver errors, available receiver buffer data, transmit buffer
empty, or when a modem status flag is detected.
-INTP
59
O
Printer Interrupt,
- This pin can be used to signal the
interrupt status of a connected printer. This pin basically
tracks the -ACK input pin, When INTSEL is a logic 0 and
interrupts are enabled by bit-4 in the control register. A
latched mode can be selected by setting INTSEL to a logic
1. In this case the interrupt -INTP is generated normally but
does not return to the inactive state until the trailing edge of
the read cycle (-IOR pin). -INTP is three stated until CON
bit-4 is set to a logic 1.
INTSEL
43
I
Interrupt Select mode - This pin selects the interrupt type for
the printer port (-INTP). When this pin is a logic 0, the
external -ACK signal state is generally followed, minus
some minor propagation delay. Making this pin a logic 1 or
connecting it to VCC will set the interrupt latched mode. In
this case the printer interrupt (-INTP) will not return to a logic
1 until the trailing edge of -IOR (end of the external CPU
read cycle).
-IOR
37
I
Read strobe.- A logic 0 transition on this pin will place the
contents of an Internal register defined by address bits A0-A2
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