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參數(shù)資料
| 型號： | ST16C452IJ68PS-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 2/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART W/PAR PORT DUAL 68PLCC |
| 標(biāo)準包裝： | 19 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 1 字節(jié) |
| 規(guī)程： | 打印機 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC |
| 包裝： | 管件 |
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10
ST16C452/452PS
Rev. 3.20
The generator divides the input 16X clock by any divisor
from 1 to 216 -1. The 452/452PS divides the basic
external clock by 16. The basic 16X clock provides table
rates to support standard and custom applications
using the same system design. The rate table is
configured via the DLL and DLM internal register func-
tions. Customized Baud Rates can be achieved by
selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the Baud Rate Generator Registers
DLM (MSB) and DLL (LSB) provides a user capability
for selecting the desired final baud rate. The example
in Table 5 below, shows the selectable baud rate table
available when using a 1.8432 MHz external clock
input.
Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK):
Output
User
DLM
DLL
Baud Rate
16 x Clock
Program
Divisor
Value
(Decimal)
(HEX)
50
2304
900
09
00
110
1047
417
04
17
150
768
300
03
00
300
384
180
01
80
600
192
C0
00
C0
1200
96
60
00
60
2400
48
30
00
30
4800
24
18
00
18
7200
16
10
00
10
9600
12
0C
00
0C
19.2k
6
06
00
06
38.4k
3
03
00
03
57.6k
2
02
00
02
115.2k
1
01
00
01
Loop-back Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. MCR register bits 0-3 are used
for controlling loop-back diagnostic testing. In the
loop-back mode INT enable and MCR bit-2 in the MCR
register (bits 2,3) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally (See Figure 6). The -CTS, -DSR, -
CD, and -RI are disconnected from their normal
modem control inputs pins, and instead are connected
internally to -DTR, -RTS, INT enable and MCR bit-2.
Loop-back test data is entered into the transmit hold-
ing register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loop-
back connection. The receive UART converts the
serial data back into parallel data that is then made
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C452IJ68TR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 3.3V/5V 68-Pin PLCC T/R 制造商:Exar Corporation 功能描述:ST16C452IJ68TR-F |
| ST16C452PS | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH PARALLEL PRINTER PORT |
| ST16C454 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| ST16C454_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| ST16C454CJ | 制造商:Exar Corporation 功能描述: |
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