參數(shù)資料
型號: ST16C450IJ44-F
廠商: Exar Corporation
文件頁數(shù): 2/28頁
文件大?。?/td> 0K
描述: IC UART SINGLE 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 1 字節(jié)
電源電壓: 2.97 V ~ 5.5 V
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
ST16C450
10
Rev. 4.20
Figure 3, EXTERNAL CRYSTAL OSCILLATOR
CONNECTION
Loopback Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. In this mode MSR bits 4-7 are
also disconnected. However, MCR register bits 0-3
can be used for controlling loop-back diagnostic test-
ing. In the loop-back mode -OP1 and -OP2 in the MCR
register (bits 0-1) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally (See Figure 4). The -CTS, -DSR, -CD,
and -RI are disconnected from their normal modem
control inputs pins, and instead are connected inter-
nally to -DTR, -RTS, -OP1 and -OP2. Loop-back test
data is entered into the transmit holding register via the
user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the
receive UART via the internal loop-back connection. The
receive UART converts the serial data back into parallel
data that is then made available at the user data
interface, D0-D7. The user optionally compares the
received data to the initial transmitted data for verifying
error free operation of the UART TX/RX circuits.
In this mode , the receiver and transmitter interrupts are
fully operational. The Modem Control Interrupts are also
operational. However, the interrupts can only be read
using lower four bits of the Modem Control Register
(MCR bits 0-3) instead of the four Modem Status
Register bits 4-7. The interrupts are still controlled by
the IER.
C1
22pF
C2
33pF
X1
1.8432 MHz
R1
50-120
R2
1M
X
T
AL1
X
T
AL2
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