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參數(shù)資料
| 型號： | ST16 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CHIP SET INTERFACE SPECIFICATION |
| 中文描述： | 芯片組接口規(guī)范 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 146K |
| 代理商： | ST16 |
3/15
FSD_CHIPSET_B/0104VP2
ST16-19RFRDCS
1.3.3 Write access chronogram
FPGA write access chronogram, for transmission FIFO or control register:
Figure 1
: FPGA write access chronogram
In figure1, two types of access are shown. The first one is a Control register access (Mic_Ctrl_Data = ’1’)
and the second one is a FIFO access (Mic_Ctrl_Data = ’0’).
1.3.4 Read access chronogram
FPGA read access chronogram, for reception FIFO or status register:
Figure 2
FPGA read acces chronogram
In the figure 2, prior to sending data the FPGA takes the Rx_IRQ_EOF line low to indicate to the MCU that
the data can be recuperated.
Data writing
Control register writing
t4
t3
Mic_Ctrl_Data
Mic_RW
Mic_Strb_b
Mic_Data(7:0)
Rx_fifo_empty
Rx_irq_eof
Tx_fifo_empty
Tx_start
t1
t2
Acquisition of the next bytes,
except the last one
Acquisition of the first byte
t6
t4
t3
Mic_Ctrl_Data
Mic_RW
Mic_Strb_b
Mic_Data(7:0)
Rx_fifo_empty
Rx_irq_eof
Tx_fifo_empty
Tx_start
t1
t2
t0
t5
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PDF描述 |
|---|---|
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| ST16010A | 1-Mbit (128K x 8) Static RAM |
| ST16012 | 18-Mbit QDR™-II SRAM 4-Word Burst Architecture |
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相關(guān)代理商/技術(shù)參數(shù) |
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| ST160/69/23 | 制造商:Block 功能描述:Control panel transformer, 160VA, 230V |
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| ST16004 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | NPN | 450V V(BR)CEO | 5A I(C) | TO-3 |
| ST16006 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | NPN | 450V V(BR)CEO | 8A I(C) | TO-3 |
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