Notes: 1. CL incluces probe and ji" />
參數(shù)資料
型號: SSTUB32S869BHLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/17頁
文件大?。?/td> 0K
描述: IC REGIST BUFF 14BIT DDR2 150BGA
產(chǎn)品變化通告: Product Discontinuation 09/Dec/2011
標(biāo)準(zhǔn)包裝: 240
類型: 緩沖器
Tx/Rx類型: LVCMOS
延遲時間: 3.0ns
電容 - 輸入: 3.5pF
電源電壓: 1.7 V ~ 1.9 V
安裝類型: 表面貼裝
封裝/外殼: 150-TFBGA
供應(yīng)商設(shè)備封裝: 150-CABGA(8x13)
包裝: 托盤
13
ICSSSTUB32S869B
Advance Information
1203—04/11/06
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR
≤10 MHz,
Zo=50
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM.
Figure 6 — Parameter M easurement I nfor mation (VDD = 1.8 V ± 0.1 V)
RL = 1000
CL = 30 pF
(see Note 1)
LOAD CIRCUIT
tw
VICR
Inpu t
VIH
VIL
VOLTAGE WAVEFORMS – PULSE DURATION
VREF
Inpu t
tsu
th
VID
VICR
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
VICR
VID
VICR
Output
VOL
VOH
VTT
tPHL
tPLH
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
tRPHL
VOL
VOH
VIL
VIH
Output
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
VDD/2
VTT
tact
tinact
LVCMOS
Input
RST#
VOLTAGE AND CURRENT WAVEFORMS
IDD
(see
Note 2)
90%
10%
INPUTS ACTIVE AND INACTIVE TIMES
0 V
VDD
Test Point
VDD/2
LVCMOS
Inp ut
RESET#
TL=350ps, 50
DUT
CK#
Out
TL
td = 350ps
=50
CK Inputs
VID
CK
RL = 100
CK
Test Point
RL = 1000
VDD
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